Damascene architecture for multilevel interconnections

Projektinformationen

DAMASCENE

ID Finanzhilfevereinbarung: FP4_25220

Projekt abgeschlossen

Startdatum 9 September 1997

Enddatum 8 März 1999

Finanziert unter

• Specific research and technological development programme in the field of information technologies, 1994-1998

Gesamtkosten

€ 6 082 000,00

EU-Beitrag

€ 3 150 000,00

Koordiniert durch

Stmicroelectronics S.A.
France

CORDIS bietet Links zu öffentlichen Ergebnissen und Veröffentlichungen von HORIZONT-Projekten.

Links zu Ergebnissen und Veröffentlichungen von RP7-Projekten sowie Links zu einigen Typen spezifischer Ergebnisse wie Datensätzen und Software werden dynamisch von OpenAIRE abgerufen.

Verwertbare Ergebnisse

DAMASCENE ARCHITECTURE FOR MULTILEVEL INTERCONNECTIONS

The main goal of the DAMASCENE project was to investigate alternative materials and architectures of interconnects for overcoming expected limitations of subquarter CMOS electronic components (in terms of manufacturing, feasibility and electrical parasitic capacitance performance). Due to its lower resistivity, copper has been chosen to replace aluminium as metal for interconnects. So, several options for copper and associated barriers depositions were investigated: full CVD (Chemical Vapour Deposition) approach including CVD barrier with CVD copper for complete pattern filling or a low- cost approach using PVD (Physical Vapour Deposition) barrier and an IMP (Ionized Metal Plasma) copper seed layer in combination with copper electroplating for interconnect groove filling. Substantial work was done on development and evaluation of CMP (Chemical Mechanical Polishing) processes for copper and conductive barrier layers. In order to prepare the next process generation, new low tolerance materials like FLARE, PBO or SILK have been investigated. An assessment of the process feasibility of these dielectrics in a DAMASCENE architecture has been done. As the patterning was supported by the contribution of the ESPRIT-ACE project, several strategies were followed to etch dual damascene structures in oxide: self- aligned dual damascene or via first dual damascene. Finally, a preferred process flow for interconnect integration has been defined by the Consortium and ST Microelectronics/GRESSI have successfully demonstrated the feasibility of a double- level metal with a copper dual damascene on a 2 cm2 electronic component.