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Interconnection materials for environmentally compatible assembly technologies


Stencil printing remains the technology route of choice for flip chip bumping because of its economical advantages over traditionally costly evaporation and electroplating processes. This paper deals with all processing facets of 6-wafer bumping of peripheral array structures at 100µm pitch. Both type 7 (2-11µm) and type 6 (5-15µm) pastes of eutectic composition Sn63/Pb37 in conjunction with electroformed stencil technology have been successfully employed for wafer bumping. Bumping using 30µm stencil thickness has yielded bump heights of 42.3±3.8µm and 43.6±3.5µm for type 7 and type 6 pastes, respectively. Alternative stencil design scenarios are exploited and it turns out that staggered designs provide effective solutions for aperture decoupling and optimization of overprinted paste volumes for peripheral ultra fine pitch configurations. Furthermore, the present study provides insights into the fundamental understanding of the printing performance of very fine pastes and contributes in defining the narrow process windows of type 6 and type 7 pastes for wafer bumping. It is shown that type 6 paste is more appropriate than type 7 for the stencil aperture dimensions used in the present study.
Test chips were bumped using lead-free soldering technology. Stencil printing of Sn95.5Ag4Cu0.5, SnCu0.7 type 6 pastes has yielded bumps of 110µm height for area-array and peripheral structures. A stencil of 80µm thickness was used and automatic printing machine was utilised. The chips were assembled on FR4 boards, which had an opening of 80-85µm in diameter. The resultant assembly gap was measured to be 90µm. For the specific assembly a tacky flux was used whereas a manual fine placer equipment was preferred for the assembly. The assemblies were under-filled using a Hysol material and an automatic Asymtek under-filler machine. The under-filled structures have been electrically tested and the integrity of the soldered joints was also by X-Ray verified. Subsequently, the assemblies are subjected to thermal cycling (-55oC-125oC), Humidity (85%RH, 85oC) and shear testing. The initial reliability testing has shown no failures whereas the shear test results evidence the good solderability of lead-free solders used in the project for Ni/Au metallisations.
Solder fatigue is one of the major failure modes in electronic components when they are subjected to cyclic changes of temperatures caused by fabrication and in practical usage environment. An extensive literature study was done to gather some relevant materials properties that describe the behaviour of these lead-free alloys. This information was used to create different Finite Element Models (FEM) in order to investigate the effect of the new lead free solder alloys on the reliability of electronic packages and develop a better understanding of the thermo-mechanical behaviour of these materials. The FEM simulation methodology for analysing the reliability life time of lead-free solders has been developed and applied to several package types: under-filled flip chip, PSGA, BGA, CSP etc. The simulation results were compared to SnPb soldered packages resulting in general trends. In addition to the FEM simulations, basic material research has been performed. One study is the brittleness behaviour of a wide variety of lead-free alternatives. The main conclusion is that the existence of Ag in lead-free solders increases the temperature at which the material becomes brittle: the higher the Ag content, the higher this temperature. This could become a serious issue for applications at extreme low conditions (e.g. SnAg5% becomes brittle below -45°C). Under temperature + vibration cycling tests, also different failure modes for lead-free joints have been found: so-called weblike cracking inside solder joints and intermetallic failures for BGA's subjected to vibration experiments.
This technology has been developed as a flip-chip interconnection of silicon dies onto printed circuit boards (PCBs) using adhesives. The technology uses a combination of non-conductive adhesives (NCA) and isotropic conductive adhesives (ICA). The principle of the technology was invented earlier and a US patent was granted for this invention. However this technology using adhesives was changed inside the IMECAT project to be used for connecting flex to glass and be more cost-effective. For this process the first step is to stencil print the ICA onto the flexible circuit board or the glass substrate and drying it without fully curing the adhesive. For cost reasons, stencil printing and drying can be done on bigger sized boards before cutting it into the final shape. In this way 1 print stroke can be used to print several substrates. After the cutting, the NCA can be dispensed onto the dried ICA in an appropriate pattern. As a final step the glass of the flexible substrates can be placed onto the adhesives, which are then cured by thermo-compression. In this way stable low resistance contacts can be achieved which are also reliable. This technology however has more process steps then using anisotropic conductive adhesives (ACA), but because the base materials in our technology are much cheaper this ICA-NCA interconnection is most likely to be more cost-effective.
In the framework of IMECAT project, the development of lead-free wafer bumping technologies such as solder paste stencil printing, electroless Ni/Au and palladium as well as electroplating Au bumping has been achieved. In specific, stencil printing of lead-free pastes such as Sn4%Ag0.5%Cu, Sn0.7%Cu, Sn3.5%Ag has been demonstrated as an effective and economical mean for wafer bumping. The feasibility of lead-free stencil printing technology was witnessed on various wafer designs with minimum pitch of 200µm for peripheral and area-array configurations. Printing using laser-cut stencils of 75µm thickness has yielded bumps with a minimum height of 110µm. The IMECAT test wafers have been bumped successfully using a laser-cut stencil of 75µm thickness and type 6 Sn4%Ag0.5%Cu solder paste (5-15µm). The chips with 200µm and 300µm pitch have a bump height of 110µm and 130µm, respectively. New development work extends to Ultra fine pitch (UFP) structures down to 100µm pitch where bump heights of 45µm have been reached using type 7 lead-free solder paste (2-11µm). The bumped chips by stencil printing have become available to the Consortium partners for assembly tests and reliability experiments. The Advanced Printing Group in the Technical University Berlin has the capability in solder paste stencil printing and reflow soldering up to 8 inches wafers at such low pitches as 80µm.
Three flip-chip interconnect test chips are developed. With these test chips we can verify the current design rules but we can also check the more advanced design rules. Per test chip group three die areas are available. Test Chip IMECAT B - Solder ball pitch: 300 micron - Solder bump opening: 80 x 80 micron Test Chip IMECAT C - Solder ball pitch: 200 micron - Solder bump opening: 80 x 80 micron Test Chip IMECAT D - Solder ball pitch: 150 micron - Solder bump opening: 50 x 50 micron Die areas available per test chip: Sub Test Chip 1 - 10 x 10 mm - 1 available per subgroup Sub Test Chip 2 - 5 x 5 mm - 4 available per subgroup Sub Test Chip 3 - 2.5 x 2.5 mm - 4 available per subgroup
The target of the project is to develop new, very fast curing NCA materials for the flip chip technology in various industrial applications. Major requirement for the development of a very, fast curing NCA system is a profile < 10 - 15sec at 180°C - 200°C. After a screening of epoxy row materials (resins and curing agents), we decided to use a bisphenolic A/F and a cycloaliphatic resin and a cationic curing agent. The main develop work after the selection of the row materials is to investigate into the interaction of the components in the system and produce a large number of samples to test the suitability for the application. The first result of the development for a NCA system is the NCA4 - 020. The properties of this adhesive were measured and tested at Heraeus and the project partners. For the NCA system the requirement of the very fast curing time at about 180°C - 200°C was fulfilled. Different results were found by the project partners for the adhesion and reliability. Potential Application - Fast connection of flip chips on different substrates (COF, COG ). End-user - Companies, which were producing smart cards, smart labels or LCDs Main innovation features - As a alternative to the usage of ACA, a much cheaper technology Market - The applications for smart labels and LCDs will be increase in the future very fast. Potential barriers - At the moment the technology for smart labels is to expensive for a high volume applications.
A technology has been developed for the flip-chip interconnection of Si dies onto printed circuit boards (PCBs) using adhesives. The technology uses a combination of non-conductive adhesives (NCA) and isotropically conductive adhesives (ICA). The principle of the technology was invented earlier and a US patent was granted for this invention. Work in the IMECAT project proved the reliability of the technology in the case that Si dies are mounted on FR4 PCB substrates with a Probimer soldermask and Ni/Au PCB contact finish. The technology consists of following steps: Application (e.g. by stencil printing) of the ICA on the PCB Drying (but not yet fully curing) of the ICA Application of the NCA e.g. by dispensing an appropriate pattern Placement of the chip Thermo-compression of the die onto the PCB Chips with contact pitches in the range of 150µm - 300µm were mounted in this way, showing initial contact resistances in the range of 3 - 10 mΩ with standard deviations of 1mΩ (depending on the contact pitch). No raise in contact resistance was observed after following reliability tests: High temperature storage: 125°C during 500h Hot humidity testing: 85% r.h. / 85°C during 500h The result can also be applied for flip-chip assembly on other types of substrates, especially for low temperature assembly on cheap plastic substrates. The same principle of assembly can potentially be used for the interconnection of a flex substrate to a display glass substrate.
The RoHs directive 2002/95/EC and the WEEE directive 2002/96/EC have been enforced in the EU. Therefore lead will be banned in many applications after July 1, 2006. Lead free solder pastes will become a new standard in the electronic industry at least after this date. The development of such lead free solder pastes was done in the IMECAT project. For standard application a solder paste was developed by using exclusively type 3 powder. The alloy used in most cases was SnAg4Cu0.5. The flux was optimised in different aspects: soldering quality, printing and slump behaviour, corrosion resistance, stability and colour of flux residues. Soldering quality was optimized by means of wetting performance and solder balling results. These tests were conducted under different conditions: 2 different profiles in air and in nitrogen. Printing behaviour was tested in most cases with an EKRA printer type X5 and a special test layout (Heraeus Benchmarker II). Important items were fine pitch capability, stencil life (viscosity change during continuous printing), cold and hot slump and print-after-wait performance. It is planned to make this paste a standard product. At the end the developed product Called F640) was benchmarked and compared with 2 different products which are already available on the market. The developed paste is made a standard product now and it is available on the open market: F640SA40C5-89M30. For wafer bumping application a lead free solder paste was developed by using exclusively type 6 solder powder. This is the finest powder specified so far in national and international standards. 4 different lead free alloys were tested: Sn96.5Ag3.5, SnAg4Cu0.5, Sn99.3Cu0.7 and SnAg3.4Bi4.8. The most promising product is based on SnAg4Cu0.5 alloy. It is made a standard product now and it is available on the open market: F510SA40C5-89S6.
The present study intends to reveal the key process issues involved in stencil printing technology for very- fine- pitch wafer bumping up to 120µm pitch. In parallel, in face of the upcoming strict regulations for introduction of lead-free back-end processes, it provides insight into printability issues of newly developed lead-free pastes and attempts a comparison with their eutectic Sn63Pb37 counterparts. Type 6 Lead-free pastes with a powder size of 5-15µm were prepared with Sn4%Ag0.5%Cu and Sn3.5%Ag compositions. Their rheological behaviour and product stability were carefully examined using as guide well established type 6 eutectic Sn63Pb37 pastes. Printing experiments have revealed the significance of stencil design parameters, print speed, print pressure, separation speed and shear thinning behaviour of the pastes to the success of the wafer printing up to 120µm pitches. Laser-cut stencils of 75µm were used for bumping of 300µm and 200µm pitch peripheral arrays. Furthermore, the study extended up to 120µm pitch peripheral and area arrays using an electroformed 30µm thick stencil. Bumping processes have yielded bump heights of 129 ± 2.6 µm and 110 ± 4.5µm for 300µm and 200µm pitch peripheral configurations, respectively. For very fine pitch structures, lead-free bumping has resulted in bump heights of 57.2±2.6µm and 41.6±2.8µm for 120µm pitch peripheral and area arrays, respectively. Cleaning of flux residues, at least for the flux used in these pastes, does not seem to differ from cleaning of the corresponding eutectic pastes. Shear tests have provided strength values of 4.26 g/ml² for the Sn4%Ag0.5%Cu bumps and 3.07 g/mil² for the Sn3.5%Ag bumps.