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New cubic silicon carbide material for innovative semiconductor devices

Risultati finali

Semiconductor device manufacturers have stringent requirements on wafer surfaces, in particular: - Low roughness (typically a few Angstrom); - No scratches visible under microscope; - Low contamination with particulates or electrically active chemical elements; - No damaged layer below the surface; - Controlled flatness. SiC presents specific challenges for polishing: as a very hard material (third only to Diamond and Boron Nitride) and chemically inert, Silicon Carbide generates exceptional difficulties for polishing, as the traditional Chemical-Mechanical Polishing (CMP) techniques used for Silicon or other established semi-conductors do not operate. NOVASiC was able to demonstrate early on that state of the art techniques developed to polish Hexagonal SiC material are not suitable for the 3C-SiC poly-type. During the SOLSiC project, NOVASiC has succeeded in developing specific processes for this material, in order to provide epi-ready surfaces to the users. State of the art specifications were obtained, featuring 3 to 5 Angstrom roughness, no scratches, ultra clean surface and no subsurface damage. The process has been demonstrated on various sizes (10x10 samples and up to 3 inch wafers), and on material from various sources: bulk 3C-SiC, free-standing material from HOYA as well as 3C-SiC on Silicon. Benefits of NOVASiC’s 3C-SiC polishing were demonstrated by leading laboratories in terms of performance and yield. Besides, the possibility to reclaim 3C wafers after defective epitaxy was demonstrated. This open the opportunity to reduce material cost for device development and further industrial device manufacturing. Building on NOVASiC’s expertise in industrial polishing of H-SiC, we are confident that the processes is suitable for volume ramp up and can be scaled up to larger diameters in order to meet future industrial applications of 3C-SiC. NOVASiC has started providing polishing service of 3C-SiC commercially to laboratories and devices manufacturers worldwide. It complements NOVASiC’s unique range of services and expertise on Silicon Carbide.
An experimental crystal growth set-up based on industrial CYBERSTAR product was developed during the project. The system alloys the growth of Silicon Carbide (SiC) crystal in a silicon float zone. The system is heated by a specific commercial generator working in the 2 MHz range. The system is equipped with primary and secondary unit pumping systems, and the atmosphere in the chamber is controlled. The upper and lower units can rotate and translate separately at a very low rate (0.01mm/h). Some specific rotation strategies can be applied in order to control the forced convection in the silicon. A two pyrometer system enables access to the thermal measurements close to the core zone where the crystallization takes place. All the basic control/commands of the system are activated by computer. The system can be used for other specific refractory crystals where a solvent is required (TiC, ZrC, etc.. ) and/or when a contact-less system (without a crucible) is necessary for chemical reasons. A specific process for growing SiC crystal in a silicon float zone based on a joint (IKZ-CEA) patent is developed. The process is first related to the preparation of the required raw materials (SiC seed and feed), the installation in the core zone, as well as all the different steps of the process including temperature management, motion controls, and atmosphere control up to the cooling of the system. The process is currently under further development in the frame-work of a PhD thesis at CEA. This process is specific for silicon carbide crystals.
The work carried out during the course of the project has advanced the overall purity of the reaction bonding technique by an order of magnitude. Improvement in purity was directly important to the project itself, but also has wider implications for the production and subsequent use of SiC. The traditional processing technique needed sintering aids; impurities which helps the material to react and form a dense body. In a range of high performance engineering applications, and also in electrical/electronic applications the addition of certain types of impurity can be problematic, so as well as producing an overall higher purity material, the technology developed through the course of the project has permitted a broader range of additives to be used, which may not be as efficient as traditional sintering aids, but avoid introducing types of contamination which are deleterious to the application in question. This has delivered potential opportunities for aerospace, automotive and electronic component manufacturers.
- SiC is known as potential material for a new generation of power devices. Hexagonal SiC polytypes seem to be more suited for high power applications (2000-10000V), while 3C-SiC is more suited for medium power applications (300-1200V, 10-100A) due to its smaller bandgap. For use in power applications, two types of devices should be available: rectifiers (diodes) and transistors (e.g. MOSFETs). Processes for both types of devices based on 3C-SiC were developed during the project and several device batches were carried out, including Schottky barrier diodes (SBD), junction-barrier controlled Schottky diodes (JBS), and pn-junction diodes (PND), as well as lateral and vertical MOSFET transistors. All these devices work in principle as they should, but not with the expected performance. Especially their blocking capability is limited to about 100V by extended crystal defects like stacking faults. It was shown during the project that material improvements by reducing the number of crystal defects will enable the use of 3C-SiC devices for at least 300-600V applications. Especially vertical MOSFET devices have been shown to be able to carry high currents with typical gate control voltages of 15-20V and on-state resistances similar to state of the art hexagonal SiC devices. - A full set of unit processes for the fabrication of 3C-SiC devices was established at ACREO. The process line includes epitaxial growth of n- and p-doped epilayers, ion implantation and post-implantation anneal, lithography, dry etching, ohmic contact formation, silicon dioxide and silicon nitride deposition, and thermal oxidation.