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Content archived on 2024-05-27

Chip interconnect with reduction of real estate using micro-substrates

Objective

The flip chip assembly process shall be made compatible with future wirebond pitches on an industrial scale. This shall result in miniature electrical modules for personal handheld applications.

The activities comprise:
- Waferscale bumping, capable for 40 micron pitch.
- Bump systems comprise NiAu, Au stud bumping and PbSn through solderjetting.
- Substrates with via and routing capability compabile with 40 micron bond pad pitch on the components (ICs).
- Substrate materials: polyamide flexible substrates, silicon substrates containing passive integration with CMOS or BiCMOS devices and glass ceramic substrates with integrated passive components.
- Fine pitch interconnect processes for personal electronics, capable of IO pitches down to 40 micron.
The processes will be based on soldering or adhesive technology, with or without underfill.

Objectives:
It is the aim of the present proposal to bring flip chip technology down to pitches of 40 ?m.

Technological objectives: To develop industrially viable waferscale bumping techniques, capable for 40 micron pitch. To develop substrates with via and routing capability compatible with the 40 micron bond pad pitch on the components (ICs). To develop thin film interconnect layers between the 500 (300) micron CSP Ball pitch and the 40 micron peripheral flip chip pitch for use in chipscale BGA packages. To develop high volume low cost fine pitch flip chip interconnect processes for personal electronics products, capable for I/O pitches down to 40 micron

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Call for proposal

Data not available

Coordinator

PHILIPS ELECTRONICS NEDERLAND B.V.
EU contribution
No data
Address
BOSCHDIJK 525
5621 JG EINDHOVEN
Netherlands

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Total cost
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Participants (6)