Ferroelectric Vertical Low energy Low latency low volume Modules fOr Neural network Transformers In 3D

Resultado final

Elementary VNWFET devices (JL and PC) - V1

Fabrication of elementary VNWFET devices (JL and PC) - First version

Elementary VNWFET devices (JL and PC) - V2

Fabrication of elementary VNWFET devices (JL and PC) - improved version

Thermal impedance and trap extraction - V1

First report on the thermal impedance and trap extraction of VNWFETs devices fabricated in WP1

Plan for dissemination of the results - Y1

Annual plan for dissemination of the results

Workshops and summer school's report

Report on workshops and summer school's

Plan for dissemination of the results - Y2

Annual plan for dissemination of the results, year 2

Technology impact and exploitation innovation - Y1

Technology impact and exploitation innovation First assessment

Pre-trained speech ASR/MT model and use-cases - V2

Second version of pre-trained speech ASR/MT model and use-cases

Open source release: parameterizable simulator with application examples - V1

First open source release: parameterizable simulator with application examples

Plan for dissemination of the results - Y3

Annual plan for dissemination of the results - year 3

Scaled-down N2C2 design

Report on scaled-down N2C2 design

Library of optimized VNWFET-based logic cells
Pre-trained speech ASR/MT model and use-cases - V1

First version of pretrained speech ASRMT model and usecases

Architecture library, multi-objective trade-offs and calibrated thermal models - V1

First version of architecture library, multi-objective trade-offs and calibrated thermal models

Technology impact and exploitation innovation - Y2

Technology impact and exploitation innovation - Second assessment

Virtual scalable N2C2 design and Pareto-front data - V1

Report on virtual scalable N2C2 design and Paretofront data V1

Co-optimized hardware/NN architecture for ASR/MT - V1

First report on the co-optimized hardware/NN architecture for ASR/MT

Versatile and scalable 3D architectural interconnect framework

Report on the versatile and scalable 3D architectural interconnect framework

Project handbook

Handbook summarizing decisionmaking process and planned meetings quality process for deliverables deliverable template progress reports template

Parasitic element extraction - V1

Report on parasitic element extraction

Project Website and social network account

Project Website and social networks accounts for FVLLMONTI are visible online

Data Management Plan

Publicaciones

Strategies for Characterization and Parameter Extraction of Vertical Junction-less Nanowire FETs dedicated to Design Technology Co-Optimization

Autores: C. Maneux, C. Mukherjee, M. Deng, G. Larrieu, Y. Wang, Houssem Rezgui and B. Neckel Wesling
Publicado en: 243rd ECS Meeting, Boston, US, May 28th -June 2nd, 2023, Edición mai-23, 2023
Editor: ECS
DOI: 10.1149/11101.0209ecst

Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors

Autores: L. Réveil, C. Mukherjee, C. Maneux, M. Deng, F. Marc, A. Kumar, A. Lecestre, G. Larrieu, A. Poittevin, I. O'Connor, O. Baumgartner and D. Pirker
Publicado en: VLSI-SOC, 2022
Editor: VLSI-SOC

Compact Metal-Ferroelectric-Insulator-Semiconductor (MFIS) Approaches Versus TCAD For the Modeling Of Ferroelectric Transistors (FeFETs): Percolation, Steep-Subthreshold and Depolarization

Autores: Thesberg, M., Schanovsky, F., Stanojevic, Z., Baumgartner, O. and Karner, M.
Publicado en: International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Edición 2023, 2023, ISBN 978-4-86348-803-8
Editor: IEEE
DOI: 10.23919/sispad57422.2023.10319645

Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge

Autores: Rios, M., Ponzina, F., Ansaloni, G., Levisse, A. and Atienza, D.
Publicado en: In Proceedings of the Great Lakes Symposium on VLSI 2022, Edición 2022, 2022, ISBN 9781450393225
Editor: Association for Computing Machinery
DOI: 10.1145/3526241.3530351

Advanced contacts on 3D nanostructured channels for vertical transport gate-all-around transistors

Autores: Guilhem Larrieu, Jonas Müller, Sylvain Pelloquin, Abhishek Kumar, Konstantinos Moustakas, Pawel Michalowski, Aurelie Lecestre
Publicado en: 21st International Workshop on Junction Technology (IWJT), Edición 23 juin, 2023, ISBN 978-4-86348-807-6
Editor: IEEE
DOI: 10.23919/iwjt59028.2023.10175172

Analysis of Energy-Delay-Product of a 3D Vertical Nanowire FET Technology

Autores: Ian O’Connor, Arnaud Poittevin, Sébastien Le Beux, Alberto Bosio, Zlatan Stanojevic, Oskar Baumgartner, C Mukherjee, C Maneux, J Trommer, T Mikolajick, G Larrieu
Publicado en: Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS), 2021, Página(s) 1-4
Editor: NA

INCLASS: incremental classification strategy for self-aware epileptic seizure detection

Autores: Ferretti, Lorenzo, Giovanni Ansaloni, Renaud Marquis, Tomas Teijeiro, Philippe Ryvlin, David Atienza, and Laura Pozzi
Publicado en: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022, Página(s) 1449-1454
Editor: IEEE

Extraction of small signal equivalent circuit for de−embedding of 3D vertical nanowire transistor

Autores: B. Neckel Wesling, M. Deng, C. Mukherjee, A. Kumar, G. Larrieu, et al.
Publicado en: 8th Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI−ULIS) 2022, May, Edición mai 22, 2022
Editor: Elsevier
DOI: 10.1016/j.sse.2022.108359

Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures

Autores: Medina Morillas, Rafael, Joshua Alexander Harrison Klein, Yasir Mahmood Qureshi, Marina Zapater Sancho, Giovanni Ansaloni, and David Atienza Alonso
Publicado en: IEEE 13th Latin America Symposium on Circuits and System (LASCAS), 2022
Editor: IEEE

Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence

Autores: C. Maneux, C. Mukherjee, M. Deng, M. Dubourg, L. Reveil, G. Bordea, A. Lecestre, G. Larrieu, J. Trommer, E.T. Breyer, S. Slesazeck, T. Mikolajick, O. Baumgartner, M. Karner, D. Pirker, Z. Stanojevic, David Atienza, A. Levisse, G. Ansaloni, A. Poittevin, A. Bosio, D. Deleruyelle, C. Marchand, I. O'Connor
Publicado en: IEEE IEDM, 2021
Editor: IEEE

Transformer model compression for end-to-end speech recognition on mobile devices

Autores: Leila Ben Letaifa, Jean-Luc Rouas.
Publicado en: EUSIPCO 2022, 2022
Editor: EUSIPCO

Circuit Design Flow dedicated to 3D vertical nanowire FET

Autores: C. Maneux, C. Mukherjee, M. Deng, B. Neckel Wesling, L. Reveil, Z. Stanojevic, O. baumgartner, A. Poittevin, I. O'Connor, G. Larrieu
Publicado en: IEEE LAEDC, 2022
Editor: NA

A Logic Cell Design and routing Methodology Specific to VNWFET

Autores: A. Poittevin, I. O‘Connor, C. Marchand, A. Bosio, C. Maneux, C. Mukherjee, G. Larrieu, A. Kumar
Publicado en: 20th IEEE Interregional NEWCAS Conference (NEWCAS), 2022
Editor: NA
DOI: 10.1109/newcas52662.2022.9842100

Demonstration of a p-type Junctionless Silicon Nanowire Transistor with Ferroelectric Hafnium-Zirkonium-Oxide Gate

Autores: T. Mauersberger, J. Trommer, G. Galderisi, M. Knaut, D. Pohl, A. Tahn, B. Rellinghaus, T. Mikolajick, A. Heinzig
Publicado en: EMRS Fall Meeting, Warsaw, 2023, Edición No proceedings, talk only, 2023
Editor: EMRS

Advancements in HZO Layer Engineering for Ultimate 3D Vertical Transistors : Towards a Logic-In-Memory Application

Autores: K. Moustakas, B. Neckel-Wesling, A. Lecestre, F. Mathieu, T. Mikolajick, J. Trommer, G. Larrieu, L. Cancellara, J.-D. Grillet
Publicado en: EMRS Fall Meeting, Warsaw, 2023, Edición 23-oct., 2023
Editor: EMRS

Understanding the substrate effect on de-embedding structures fabricated on SOI wafers using electromagnetic simulation

Autores: B. Neckel Wesling, M. Deng, C. Mukherjee, T. Mikolajick, J. Trommer and C. Maneux
Publicado en: IEEE International Conference on Microelectronic Test Structures (ICMTS), April 2024, Edinburgh, Scotland, Edición Avr 24, 2024
Editor: IEEE

Thermal consideration in nanoscale gate-all-around vertical transistors

Autores: Guilhem Larrieu, Houssem Rezgui, Abhishek Kumar, Jonas Müller, Sylvain Pelloquin, Yifan Wang, Marina Deng, Aurelie Lecestre, Cristell Maneux, Chhandak Mukherjee
Publicado en: 2023 Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, Edición juin-23, 2023, ISBN 978-4-86348-808-3
Editor: IEEE
DOI: 10.23919/snw57900.2023.10183951

INCLASS: Incremental Classification Strategy for Self-Aware Epileptic Seizure Detection

Autores: Lorenzo Ferretti; Giovanni Ansaloni; Renaud Marquis; Tomas Teijeiro; Philippe Ryvlin; David Atienza; Laura Pozzi
Publicado en: 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), Edición 1, 2022, Página(s) 1449-1454
Editor: IEEE
DOI: 10.23919/date54114.2022.9774713

Fine-grained analysis of the transformer model for efficient pruning

Autores: L. Ben Letaifa and J.-L. Rouas
Publicado en: 21st IEEE International Conference on Machine Learning and Applications (ICMLA), Dec. 2022, Edición 2022, 2022
Editor: IEEE
DOI: 10.1109/icmla55696.2022.00149

Overflow-free compute memories for edge AI acceleration

Autores: Ponzina F, Rios M, Levisse A, Ansaloni G, Atienza D.
Publicado en: ACM Transactions on Embedded Computing Systems, Edición ACM Transactions on Embedded Computing SystemsVolume 22Edición 5sArticle No.: 121, 2023, Página(s) pp 1–23, ISSN 1539-9087
Editor: Association for Computing Machinary, Inc.
DOI: 10.1145/3609387

Single-step reactive ion etching process for device integration of hafnium-zirconium-oxide (HZO)/titanium nitride (TiN) stacks

Autores: Tom Mauersberger; Jens Trommer; Saurabh Sharma; Martin Knaut; Darius Pohl; Bernd Rellinghaus; Thomas Mikolajick; Andre Heinzig
Publicado en: Semiconductor Science and Technology, Edición 1, 2021, ISSN 0268-1242
Editor: Institute of Physics Publishing
DOI: 10.1088/1361-6641/ac1827

A hardware/software co-design vision for deep learning at the edge

Autores: Ponzina, Flavio, Simone Machetti, Marco Antonio Rios, Benoît Walter Denkinger, Alexandre Sébastien Julien Levisse, Giovanni Ansaloni, Miguel Peon Quiros, and David Atienza Alonso
Publicado en: IEEE Micro - Special Edición on Artificial Intelligence at the Edge, 2022, ISSN 0272-1732
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/mm.2022.3195617

Compact modeling of 3D vertical junctionless gate-all-around silicon nanowire transistors towards 3D logic design

Autores: Mukherjee, C., Poittevin, A., O'Connor, I., Larrieu, G., Maneux, C.
Publicado en: Solid-State Electronics, 2021, ISSN 0038-1101
Editor: Pergamon Press Ltd.
DOI: 10.1016/j.sse.2021.108125

Nanoscale Thermal Transport in Vertical Gate-all-around Junction-less Nanowire Transistors - Part I: Experimental Methods

Autores: C. Mukherjee, H. Rezgui, Y. Wang, M. Deng, A. Kumar, J. Muller, G. Larrieu and C. Maneux
Publicado en: IEEE TED Vol 70 n°12, Edición 11 oct, 2023, ISSN 0018-9383
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ted.2023.3321277

Nanoscale Thermal Transport in Vertical Gate-all-around Junction-less Nanowire Transistors- Part II: Multiphysics Simulation

Autores: H. Rezgui, C. Mukherjee, Y. Wang, M. Deng, A. Kumar, J. Muller, G. Larrieu and C. Maneux
Publicado en: IEEE TED Vol 70 n°12, Edición oct.-23, 2023, ISSN 0018-9383
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ted.2023.3321280

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