Ferroelectric Vertical Low energy Low latency low volume Modules fOr Neural network Transformers In 3D

Risultati finali

Elementary VNWFET devices (JL and PC) - V1

Fabrication of elementary VNWFET devices (JL and PC) - First version

Elementary VNWFET devices (JL and PC) - V2

Fabrication of elementary VNWFET devices (JL and PC) - improved version

Thermal impedance and trap extraction - V1

First report on the thermal impedance and trap extraction of VNWFETs devices fabricated in WP1

Plan for dissemination of the results - Y1

Annual plan for dissemination of the results

Workshops and summer school's report

Report on workshops and summer school's

Plan for dissemination of the results - Y2

Annual plan for dissemination of the results, year 2

Technology impact and exploitation innovation - Y1

Technology impact and exploitation innovation First assessment

Pre-trained speech ASR/MT model and use-cases - V2

Second version of pre-trained speech ASR/MT model and use-cases

Open source release: parameterizable simulator with application examples - V1

First open source release: parameterizable simulator with application examples

Plan for dissemination of the results - Y3

Annual plan for dissemination of the results - year 3

Scaled-down N2C2 design

Report on scaled-down N2C2 design

Library of optimized VNWFET-based logic cells
Pre-trained speech ASR/MT model and use-cases - V1

First version of pretrained speech ASRMT model and usecases

Architecture library, multi-objective trade-offs and calibrated thermal models - V1

First version of architecture library, multi-objective trade-offs and calibrated thermal models

Technology impact and exploitation innovation - Y2

Technology impact and exploitation innovation - Second assessment

Virtual scalable N2C2 design and Pareto-front data - V1

Report on virtual scalable N2C2 design and Paretofront data V1

Co-optimized hardware/NN architecture for ASR/MT - V1

First report on the co-optimized hardware/NN architecture for ASR/MT

Versatile and scalable 3D architectural interconnect framework

Report on the versatile and scalable 3D architectural interconnect framework

Project handbook

Handbook summarizing decisionmaking process and planned meetings quality process for deliverables deliverable template progress reports template

Parasitic element extraction - V1

Report on parasitic element extraction

Project Website and social network account

Project Website and social networks accounts for FVLLMONTI are visible online

Data Management Plan

Pubblicazioni

Strategies for Characterization and Parameter Extraction of Vertical Junction-less Nanowire FETs dedicated to Design Technology Co-Optimization

Autori: C. Maneux, C. Mukherjee, M. Deng, G. Larrieu, Y. Wang, Houssem Rezgui and B. Neckel Wesling
Pubblicato in: 243rd ECS Meeting, Boston, US, May 28th -June 2nd, 2023, Numero mai-23, 2023
Editore: ECS
DOI: 10.1149/11101.0209ecst

Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors

Autori: L. Réveil, C. Mukherjee, C. Maneux, M. Deng, F. Marc, A. Kumar, A. Lecestre, G. Larrieu, A. Poittevin, I. O'Connor, O. Baumgartner and D. Pirker
Pubblicato in: VLSI-SOC, 2022
Editore: VLSI-SOC

Compact Metal-Ferroelectric-Insulator-Semiconductor (MFIS) Approaches Versus TCAD For the Modeling Of Ferroelectric Transistors (FeFETs): Percolation, Steep-Subthreshold and Depolarization

Autori: Thesberg, M., Schanovsky, F., Stanojevic, Z., Baumgartner, O. and Karner, M.
Pubblicato in: International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Numero 2023, 2023, ISBN 978-4-86348-803-8
Editore: IEEE
DOI: 10.23919/sispad57422.2023.10319645

Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge

Autori: Rios, M., Ponzina, F., Ansaloni, G., Levisse, A. and Atienza, D.
Pubblicato in: In Proceedings of the Great Lakes Symposium on VLSI 2022, Numero 2022, 2022, ISBN 9781450393225
Editore: Association for Computing Machinery
DOI: 10.1145/3526241.3530351

Advanced contacts on 3D nanostructured channels for vertical transport gate-all-around transistors

Autori: Guilhem Larrieu, Jonas Müller, Sylvain Pelloquin, Abhishek Kumar, Konstantinos Moustakas, Pawel Michalowski, Aurelie Lecestre
Pubblicato in: 21st International Workshop on Junction Technology (IWJT), Numero 23 juin, 2023, ISBN 978-4-86348-807-6
Editore: IEEE
DOI: 10.23919/iwjt59028.2023.10175172

Analysis of Energy-Delay-Product of a 3D Vertical Nanowire FET Technology

Autori: Ian O’Connor, Arnaud Poittevin, Sébastien Le Beux, Alberto Bosio, Zlatan Stanojevic, Oskar Baumgartner, C Mukherjee, C Maneux, J Trommer, T Mikolajick, G Larrieu
Pubblicato in: Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS), 2021, Pagina/e 1-4
Editore: NA

INCLASS: incremental classification strategy for self-aware epileptic seizure detection

Autori: Ferretti, Lorenzo, Giovanni Ansaloni, Renaud Marquis, Tomas Teijeiro, Philippe Ryvlin, David Atienza, and Laura Pozzi
Pubblicato in: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022, Pagina/e 1449-1454
Editore: IEEE

Extraction of small signal equivalent circuit for de−embedding of 3D vertical nanowire transistor

Autori: B. Neckel Wesling, M. Deng, C. Mukherjee, A. Kumar, G. Larrieu, et al.
Pubblicato in: 8th Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI−ULIS) 2022, May, Numero mai 22, 2022
Editore: Elsevier
DOI: 10.1016/j.sse.2022.108359

Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures

Autori: Medina Morillas, Rafael, Joshua Alexander Harrison Klein, Yasir Mahmood Qureshi, Marina Zapater Sancho, Giovanni Ansaloni, and David Atienza Alonso
Pubblicato in: IEEE 13th Latin America Symposium on Circuits and System (LASCAS), 2022
Editore: IEEE

Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence

Autori: C. Maneux, C. Mukherjee, M. Deng, M. Dubourg, L. Reveil, G. Bordea, A. Lecestre, G. Larrieu, J. Trommer, E.T. Breyer, S. Slesazeck, T. Mikolajick, O. Baumgartner, M. Karner, D. Pirker, Z. Stanojevic, David Atienza, A. Levisse, G. Ansaloni, A. Poittevin, A. Bosio, D. Deleruyelle, C. Marchand, I. O'Connor
Pubblicato in: IEEE IEDM, 2021
Editore: IEEE

Transformer model compression for end-to-end speech recognition on mobile devices

Autori: Leila Ben Letaifa, Jean-Luc Rouas.
Pubblicato in: EUSIPCO 2022, 2022
Editore: EUSIPCO

Circuit Design Flow dedicated to 3D vertical nanowire FET

Autori: C. Maneux, C. Mukherjee, M. Deng, B. Neckel Wesling, L. Reveil, Z. Stanojevic, O. baumgartner, A. Poittevin, I. O'Connor, G. Larrieu
Pubblicato in: IEEE LAEDC, 2022
Editore: NA

A Logic Cell Design and routing Methodology Specific to VNWFET

Autori: A. Poittevin, I. O‘Connor, C. Marchand, A. Bosio, C. Maneux, C. Mukherjee, G. Larrieu, A. Kumar
Pubblicato in: 20th IEEE Interregional NEWCAS Conference (NEWCAS), 2022
Editore: NA
DOI: 10.1109/newcas52662.2022.9842100

Demonstration of a p-type Junctionless Silicon Nanowire Transistor with Ferroelectric Hafnium-Zirkonium-Oxide Gate

Autori: T. Mauersberger, J. Trommer, G. Galderisi, M. Knaut, D. Pohl, A. Tahn, B. Rellinghaus, T. Mikolajick, A. Heinzig
Pubblicato in: EMRS Fall Meeting, Warsaw, 2023, Numero No proceedings, talk only, 2023
Editore: EMRS

Advancements in HZO Layer Engineering for Ultimate 3D Vertical Transistors : Towards a Logic-In-Memory Application

Autori: K. Moustakas, B. Neckel-Wesling, A. Lecestre, F. Mathieu, T. Mikolajick, J. Trommer, G. Larrieu, L. Cancellara, J.-D. Grillet
Pubblicato in: EMRS Fall Meeting, Warsaw, 2023, Numero 23-oct., 2023
Editore: EMRS

Understanding the substrate effect on de-embedding structures fabricated on SOI wafers using electromagnetic simulation

Autori: B. Neckel Wesling, M. Deng, C. Mukherjee, T. Mikolajick, J. Trommer and C. Maneux
Pubblicato in: IEEE International Conference on Microelectronic Test Structures (ICMTS), April 2024, Edinburgh, Scotland, Numero Avr 24, 2024
Editore: IEEE

Thermal consideration in nanoscale gate-all-around vertical transistors

Autori: Guilhem Larrieu, Houssem Rezgui, Abhishek Kumar, Jonas Müller, Sylvain Pelloquin, Yifan Wang, Marina Deng, Aurelie Lecestre, Cristell Maneux, Chhandak Mukherjee
Pubblicato in: 2023 Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, Numero juin-23, 2023, ISBN 978-4-86348-808-3
Editore: IEEE
DOI: 10.23919/snw57900.2023.10183951

INCLASS: Incremental Classification Strategy for Self-Aware Epileptic Seizure Detection

Autori: Lorenzo Ferretti; Giovanni Ansaloni; Renaud Marquis; Tomas Teijeiro; Philippe Ryvlin; David Atienza; Laura Pozzi
Pubblicato in: 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), Numero 1, 2022, Pagina/e 1449-1454
Editore: IEEE
DOI: 10.23919/date54114.2022.9774713

Fine-grained analysis of the transformer model for efficient pruning

Autori: L. Ben Letaifa and J.-L. Rouas
Pubblicato in: 21st IEEE International Conference on Machine Learning and Applications (ICMLA), Dec. 2022, Numero 2022, 2022
Editore: IEEE
DOI: 10.1109/icmla55696.2022.00149

Overflow-free compute memories for edge AI acceleration

Autori: Ponzina F, Rios M, Levisse A, Ansaloni G, Atienza D.
Pubblicato in: ACM Transactions on Embedded Computing Systems, Numero ACM Transactions on Embedded Computing SystemsVolume 22Numero 5sArticle No.: 121, 2023, Pagina/e pp 1–23, ISSN 1539-9087
Editore: Association for Computing Machinary, Inc.
DOI: 10.1145/3609387

Single-step reactive ion etching process for device integration of hafnium-zirconium-oxide (HZO)/titanium nitride (TiN) stacks

Autori: Tom Mauersberger; Jens Trommer; Saurabh Sharma; Martin Knaut; Darius Pohl; Bernd Rellinghaus; Thomas Mikolajick; Andre Heinzig
Pubblicato in: Semiconductor Science and Technology, Numero 1, 2021, ISSN 0268-1242
Editore: Institute of Physics Publishing
DOI: 10.1088/1361-6641/ac1827

A hardware/software co-design vision for deep learning at the edge

Autori: Ponzina, Flavio, Simone Machetti, Marco Antonio Rios, Benoît Walter Denkinger, Alexandre Sébastien Julien Levisse, Giovanni Ansaloni, Miguel Peon Quiros, and David Atienza Alonso
Pubblicato in: IEEE Micro - Special Numero on Artificial Intelligence at the Edge, 2022, ISSN 0272-1732
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/mm.2022.3195617

Compact modeling of 3D vertical junctionless gate-all-around silicon nanowire transistors towards 3D logic design

Autori: Mukherjee, C., Poittevin, A., O'Connor, I., Larrieu, G., Maneux, C.
Pubblicato in: Solid-State Electronics, 2021, ISSN 0038-1101
Editore: Pergamon Press Ltd.
DOI: 10.1016/j.sse.2021.108125

Nanoscale Thermal Transport in Vertical Gate-all-around Junction-less Nanowire Transistors - Part I: Experimental Methods

Autori: C. Mukherjee, H. Rezgui, Y. Wang, M. Deng, A. Kumar, J. Muller, G. Larrieu and C. Maneux
Pubblicato in: IEEE TED Vol 70 n°12, Numero 11 oct, 2023, ISSN 0018-9383
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ted.2023.3321277

Nanoscale Thermal Transport in Vertical Gate-all-around Junction-less Nanowire Transistors- Part II: Multiphysics Simulation

Autori: H. Rezgui, C. Mukherjee, Y. Wang, M. Deng, A. Kumar, J. Muller, G. Larrieu and C. Maneux
Pubblicato in: IEEE TED Vol 70 n°12, Numero oct.-23, 2023, ISSN 0018-9383
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ted.2023.3321280

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