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Engineering low power tunnel transistors based on two-dimensional semiconductors

Periodic Reporting for period 2 - 2D-LOTTO (Engineering low power tunnel transistors based on two-dimensional semiconductors)

Berichtszeitraum: 2023-03-01 bis 2024-08-31

Vertical integration of atomically thin semiconductors for ultra-low power electronics

The metal-oxide semiconductor field-effect transistor (MOSFET) is the most widely used FET. The tunnel FET, an experimental type of transistor, can overcome this limitation by leveraging quantum mechanical tunnelling. The EU-funded 2D-LOTTO project addresses key challenges that limit the realisation of high-performance tunnel FETs. The project deals with integration of low-resistance p- and n-type contacts, high k-dielecric materials and 2D vertical semiconductor heterostructures with ideal interfaces that provide ultra-low power, CMOS-compatible tunnel FETs. The aim is to transform IoT, Big Data and computing.
Recent progress on the project has been to realise ultra-clean and low resistance p-type van der Waals contacts (Nature 2022), wafer scale growth of hBN (Nature 2022), ferroelectric heterostructures of MoS2/WS2 (Science 2022), vdW contacts as tunnel barriers for spin injection (Nature Electronics, under revision), and ideal high k-dielectrics for 2D semiconductors and their heterostructures (Nature, under revision). In the last phase of the project, we will integrate these discoveries to realise devices based on heterostructures (initial results are published in Nano Lett.2024).
The results outlined in the report and some of the papers are considered to be major breakthroughs in the field and therefore by definition are beyond the state-of-the-art.
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