Real Processing in Phase Change Memory

Project Information

Real-PCM-PIM

Grant agreement ID: 101069336

DOI

10.3030/101069336

Project closed

EC signature date 22 March 2022

Start date 1 April 2022

End date 30 September 2023

Funded under

• European Research Council (ERC)

Total cost

No data

EU contribution

€ 150 000,00

Coordinated by

TECHNION - ISRAEL INSTITUTE OF TECHNOLOGY
Israel

CORDIS provides links to public deliverables and publications of HORIZON projects.

Links to deliverables and publications from FP7 projects, as well as links to some specific result types such as dataset and software, are dynamically retrieved from OpenAIRE .

Deliverables

Documents, reports (1)

Data Management Plan

Drafting of Data Management Plan

Publications

Peer reviewed articles (4)

AritPIM: High-Throughput In-Memory Arithmetic

Author(s): Orian Leitersdorf; Dean Leitersdorf; Jonathan Gal; Mor Dahan; Ronny Ronen; Shahar Kvatinsky
Published in: IEEE Transactions on Emerging Topics in Computing (TETC), 2023, ISSN 2168-6750
Publisher: IEEE Computer Society
DOI: 10.1109/TETC.2023.3268137

FourierPIM: High-throughput in-memory Fast Fourier Transform and polynomial multiplication

Author(s): Orian Leitersdorf, Yahav Boneh, Gonen Gazit, Ronny Ronen, Shahar Kvatinsky
Published in: Memories - Materials, Devices, Circuits and Systems, 2023, ISSN 2773-0646
Publisher: Elsevier
DOI: 10.48550/arXiv.2304.02336

Stateful Logic Using Phase Change Memory

Author(s): Hoffer, Barak; Wainstein, Nicolas; Neumann, Christopher M.; Pop, Eric; Yalon, Eilam; Kvatinsky, Shahar; Hoffer, Barak
Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2022, ISSN 2329-9231
Publisher: IEEE
DOI: 10.48550/arXiv.2212.14377

Experimental Demonstration of Non-Stateful In-Memory Logic with 1T1R OxRAM Valence Change Mechanism Memristors

Author(s): Henriette Padberg, Amir Regev, Giuseppe Piccolboni, Alessandro Bricalli, Gabriel Molas, Jean Francois Nodin, Shahar Kvatinsky
Published in: IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, ISSN 1558-3791
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.48550/arXiv.2310.16843

Conference proceedings (4)

On Consistency for Bulk-Bitwise Processing-in-Memory

Author(s): B. Perach, R. Ronen, and S. Kvatinsky
Published in: 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023, ISSN 2378-203X
Publisher: IEEE
DOI: 10.48550/arXiv.2211.07542

Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory

Author(s): Perach, Ben; Ronen, Ronny; Kvatinsky, Shahar
Published in: IEEE International System-on-Chip Conference (SOCC), 2023, ISSN 2164-1706
Publisher: IEEE
DOI: 10.48550/arXiv.2302.01675

Performing Stateful Logic Using Spin-Orbit Torque (SOT) MRAM

Author(s): Barak Hoffer, Shahar Kvatinsky
Published in: IEEE International Conference on Nanotechnology (NANO), 2022
Publisher: IEEE
DOI: 10.48550/arXiv.2208.00741

Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory

Author(s): Ben Perach, Ronny Ronen, Shahar Kvatinsky
Published in: IEEE interregional NEWCAS Conference, 2023, ISBN 979-8-3503-0024-6
Publisher: IEEE
DOI: 10.48550/arXiv.2307.00658