Periodic Reporting for period 1 - PHORMIC (Wafer-scale platform for Photonic Programmable Multipurpose Integrated Circuits)
Periodo di rendicontazione: 2022-10-01 al 2023-09-30
The first tier is a photonic chip platform, based on 200 mm wafer-scale silicon photonics augmented with transfer-printed III-V optical amplifiers and compact low-power MEMS actuators. The devices are encapsulated in wafer-scale hermetically sealed cavities that will also be used for on-chip gas cells that act as an absolute calibration reference for the on-chip widely tunable lasers. The combination of high-speed silicon photonics, broadband optical gain and low-power MEMS tuners is a true enabler for new applications. The process flow is supported by a design kit for building complex photonic circuits.
The second tier supplements the photonic chips with modular packaging processes and driver electronics (including high-speed drivers), and the packaging and connectivity logic are integrated in the design kit. This provides a low-threshold entry point for building complex photonic chip-based systems with active control and programmability.
The third tier creates a multipurpose programmable photonic processor, which can control the flow of light in an analogue way through a software interface. This chip, together with its electronics and programming framework, forms a true “photonics development kit”. This enables an off-the-shelf use model like that of electronic FPGAs, reducing prototyping time for new concepts from more than a year to weeks.
The PHORMIC consortium has all expertise to establish a full supply chain, including a migration path to a European industrial 200 mm foundry. The application potential of the three tiers of the platform is validated through three demonstrators, in datacenter communication, sensing and mm-wave wireless beamforming. For each case, a custom-designed chip will be compared to the multipurpose photonic processor.
A complete process flow for the integration of transfer printed III-V amplifiers and free-standing, hermetically sealed MEMS was elaborated, building on the experience from earlier projects such as MORPHIC and MICROPRINCE. Based on the new process flow, device designs were (re)optimized and embedded in a process design kit that could be used by circuit designers to build test circuits for the future demonstrators. This culminated in a tape-out of a chip design with >100 experiments uniquely enabled by this new technology platform, including a multi-purpose programmable waveguide mesh.