Periodic Reporting for period 1 - 14ACMOS (14 Anstrom CMOS IC technology)
Periodo di rendicontazione: 2022-12-01 al 2023-11-30
The 14ACMOS project enables the IC industry to migrate to the next technology node. The project is to explore and realize solutions for the manufacture of 14 Angstrom CMOS chip technology, addressing: Lithography, Metrology, Mask Infrastructure and Process technology.
The project will support the partners and their supplier networks to stay at the leading edge of high-tech developments, crucial to meet the digitization challenges of the European society. In regard to:
Scientific: Demonstrate a cost-efficient solution for 14A technology node, shifting the technological boundaries and understanding of new 14A technology nodes, including lithography, 3D metrology, characterization, masks equipment, design and process technology
Economic: Boost industrial competitiveness in the EU, stimulating job growth in a broad ecosystem consisting of large industrial and SME, OEMs, joint development partners and suppliers as well as knowledge institutes to continue the developments of new processes and modules for advanced nodes technologies. 14ACMOS will generate new partnerships, businesses and create new jobs, and attract talents in Europe.
Societal: Enabling new application in areas such as security, communication and enabling of further automation in mobility, health and research. With respect to sustainability, 14ACMOS will develop more sustainable material and processing alternatives in addition to a reduced carbon footprint of the EUV-chips.
The project will support the partners and their supplier networks to stay at the leading edge of high-tech developments, crucial to meet the digitization challenges of the European society. In regard to:
Scientific: Demonstrate a cost-efficient solution for 14A technology node, shifting the technological boundaries and understanding of new 14A technology nodes, including lithography, 3D metrology, characterization, masks equipment, design and process technology
Economic: Boost industrial competitiveness in the EU, stimulating job growth in a broad ecosystem consisting of large industrial and SME, OEMs, joint development partners and suppliers as well as knowledge institutes to continue the developments of new processes and modules for advanced nodes technologies. 14ACMOS will generate new partnerships, businesses and create new jobs, and attract talents in Europe.
Societal: Enabling new application in areas such as security, communication and enabling of further automation in mobility, health and research. With respect to sustainability, 14ACMOS will develop more sustainable material and processing alternatives in addition to a reduced carbon footprint of the EUV-chips.
In Lithography, progress has been made on improving the dynamics of the projection optics and the scanner for improved overlay at higher source power and accelerations. A test setup has been developed to investigate the impact of vibrations during operation. In addition, work started to improving serviceability of the projection optics.
Work on energy efficiency, is about enabling use of tempered cooling water, work started on improving heat transfer and cooling efficiency and development of amplifier boards to improve power efficiency and reliability.
For characterization of the EUV scanner conditions, a time-resolved spectrometer has been designed, see Figure 1. A full-scale plasma model is being validated for scanner conditions. On diagnostics, work started on a tool to measure ion energies and fluxes, even within the EUV beam. Also, work started on an improved Residual Gas Analyzer.
In metrology, Bruker started with an assessment of a novel laser-based X-ray source, aimed to improve brightness. EXCILLUM is developing a new Xray source to increase throughput, its performance baseline was confirmed.
Applied Materials Israel (AMIL) is developing an E-beam metrology and inspection platform with improved imaging and throughput. PRODRIVE prepared a pre-study on fast data storage.
PI is developing a novel wafer stage and proposes a new piezo motor technology. NOVA started the development of new Spectral Interferometry channel for optical CD metrology.
NFI is developing probe-based metrology algorithms to increase resolution and throughput and focused on Scan Probe Microscope (SPM) tip deconvolution and the removal of measurement artifacts, see Figure 2.
KLA is developing machine learning based overlay to improved total measurements uncertainties. Imec coordinated the first development of novel and refined metrology techniques for the assessment of EUV reticle degradation.
TNO validated waterjet dicing for EUV reticles and UPB found the chemical composition of the layers by Energy Dispersive X-ray metrology (EDX) investigation on EUV reticle sample and PTB has performed reference measurements for reticle degradation on EUVR.
In Mask Infrastructure, work on improving automation of the ZEISS particle removal tool (PRT) started. By combining SEM and a nanomanipulator the PRT allows removing soft particles from photomasks, see Figure 3. Work was done on development of a new manipulator and on improving reliability of the PRT by new automation features and a new common mask loader interface.
UPB worked on developing advanced mask characterization techniques. EDX analysis was successfully performed on a Cr based reticle before and after carbon deposition.
On mask repair durability against H2 plasma conditions and EUV exposure, test conditions have been defined. Work by TNO and ASML in optimizing scanner-like conditions on mask level in the TNO EUV beamline and plasma setups has started.
Further work was done on TEM lamellae preparation by focused ion-beam (FIB) from a full mask followed by investigation of the chemical composition.
In Process Technology, progress related to “Patterning solutions” comprises the identification of mature resists (Figure 4), mask tape-out and first experiments for validating half field stitching for application for 0.55NA EUV lithography.
In “Device selection”, key results include process and module development, up till the RMG module, for monolithic CFET device (Figure 5). Process development, integration options selection is enabled via next generation materials (Figure 6), hardware (wafer sorter, etch-, deposition-, metrology equipment) and EDA tooling.
In “Performant middle-of-line” (MOL) and “back-end-of-line (BEOL)” progress comprises completion of process development for Vertical-Horizontal-Vertical (VHV) scaling booster (Figure 7), the setup of materials – interfaces – deposition – analysis – system (MIDAS) infrastructure for studying binary and ternary metals for low resistive interconnects and, process simulations for 14A node BEOL with scaled pitch, down to 16nm, and airgap isolation.
Related to “Backside interconnects and functional backside” PPA (Power Performance Area) a benchmark study of different options for (partial) backside clock networks was conducted.
The work related to “Sustainable Semiconductor Technology and Systems” yielded a virtual fab model to assess ecological footprint of IC manufacturing. Application domain was extended to include logic, memory and RF chips/applications (Figure 8).
Work on energy efficiency, is about enabling use of tempered cooling water, work started on improving heat transfer and cooling efficiency and development of amplifier boards to improve power efficiency and reliability.
For characterization of the EUV scanner conditions, a time-resolved spectrometer has been designed, see Figure 1. A full-scale plasma model is being validated for scanner conditions. On diagnostics, work started on a tool to measure ion energies and fluxes, even within the EUV beam. Also, work started on an improved Residual Gas Analyzer.
In metrology, Bruker started with an assessment of a novel laser-based X-ray source, aimed to improve brightness. EXCILLUM is developing a new Xray source to increase throughput, its performance baseline was confirmed.
Applied Materials Israel (AMIL) is developing an E-beam metrology and inspection platform with improved imaging and throughput. PRODRIVE prepared a pre-study on fast data storage.
PI is developing a novel wafer stage and proposes a new piezo motor technology. NOVA started the development of new Spectral Interferometry channel for optical CD metrology.
NFI is developing probe-based metrology algorithms to increase resolution and throughput and focused on Scan Probe Microscope (SPM) tip deconvolution and the removal of measurement artifacts, see Figure 2.
KLA is developing machine learning based overlay to improved total measurements uncertainties. Imec coordinated the first development of novel and refined metrology techniques for the assessment of EUV reticle degradation.
TNO validated waterjet dicing for EUV reticles and UPB found the chemical composition of the layers by Energy Dispersive X-ray metrology (EDX) investigation on EUV reticle sample and PTB has performed reference measurements for reticle degradation on EUVR.
In Mask Infrastructure, work on improving automation of the ZEISS particle removal tool (PRT) started. By combining SEM and a nanomanipulator the PRT allows removing soft particles from photomasks, see Figure 3. Work was done on development of a new manipulator and on improving reliability of the PRT by new automation features and a new common mask loader interface.
UPB worked on developing advanced mask characterization techniques. EDX analysis was successfully performed on a Cr based reticle before and after carbon deposition.
On mask repair durability against H2 plasma conditions and EUV exposure, test conditions have been defined. Work by TNO and ASML in optimizing scanner-like conditions on mask level in the TNO EUV beamline and plasma setups has started.
Further work was done on TEM lamellae preparation by focused ion-beam (FIB) from a full mask followed by investigation of the chemical composition.
In Process Technology, progress related to “Patterning solutions” comprises the identification of mature resists (Figure 4), mask tape-out and first experiments for validating half field stitching for application for 0.55NA EUV lithography.
In “Device selection”, key results include process and module development, up till the RMG module, for monolithic CFET device (Figure 5). Process development, integration options selection is enabled via next generation materials (Figure 6), hardware (wafer sorter, etch-, deposition-, metrology equipment) and EDA tooling.
In “Performant middle-of-line” (MOL) and “back-end-of-line (BEOL)” progress comprises completion of process development for Vertical-Horizontal-Vertical (VHV) scaling booster (Figure 7), the setup of materials – interfaces – deposition – analysis – system (MIDAS) infrastructure for studying binary and ternary metals for low resistive interconnects and, process simulations for 14A node BEOL with scaled pitch, down to 16nm, and airgap isolation.
Related to “Backside interconnects and functional backside” PPA (Power Performance Area) a benchmark study of different options for (partial) backside clock networks was conducted.
The work related to “Sustainable Semiconductor Technology and Systems” yielded a virtual fab model to assess ecological footprint of IC manufacturing. Application domain was extended to include logic, memory and RF chips/applications (Figure 8).
As of yet there are no publishable results beyond the state of the art in Lithography and Metrology.
In Mask Infrastructure there is soft particles removal. Another advancement is the reduction of necessary operator inputs during operation and therefor throughput and removal success. Reliability and uptime of the system are improved by new automation features preventing mask and manipulator tip damage.
TNO will go beyond state-of-the art by closer matching the test conditions to scanner-like conditions at mask level in the TNO EUV beamline and plasma setups. In addition, TNO will improve understanding of durability aspects of mask repair and cleaning.
In Process Technology, results beyond the state-of-the-art are mask design, overlay markers/strategy for half field stitching for 0.55NA EUV lithography. Next generation materials, hardware to tackle process development challenges related to CFET device integration. Demonstration (morphological) of monolithic CFET device at aggressive pitch. Development of VHV scaling booster for enabling 4Track logic cell lay-out for cell area scaling. EDA solutions for benchmarking, at chip level, options for backside clock network. Development of a comprehensive virtual fab model, open to the public, for assessing ecological footprint of IC manufacturing.
In Mask Infrastructure there is soft particles removal. Another advancement is the reduction of necessary operator inputs during operation and therefor throughput and removal success. Reliability and uptime of the system are improved by new automation features preventing mask and manipulator tip damage.
TNO will go beyond state-of-the art by closer matching the test conditions to scanner-like conditions at mask level in the TNO EUV beamline and plasma setups. In addition, TNO will improve understanding of durability aspects of mask repair and cleaning.
In Process Technology, results beyond the state-of-the-art are mask design, overlay markers/strategy for half field stitching for 0.55NA EUV lithography. Next generation materials, hardware to tackle process development challenges related to CFET device integration. Demonstration (morphological) of monolithic CFET device at aggressive pitch. Development of VHV scaling booster for enabling 4Track logic cell lay-out for cell area scaling. EDA solutions for benchmarking, at chip level, options for backside clock network. Development of a comprehensive virtual fab model, open to the public, for assessing ecological footprint of IC manufacturing.