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Contenido archivado el 2024-06-18

Efficient Silicon Multi-Chip System-in-Package Integration - Reliability, Failure Analysis and Test

Objetivo

The ENIAC JU project ESiP is addressing the issues of reliability, failure analysis and testing in innovative system-in-package (SiP) solutions. Highly integrated systems with greater miniaturisation and increased functionality open new markets and improve the quality of life through a wide range of applications. In particular, higher systems integration technologies using multi-chip packaging, through-silicon via technologies or package-stacking approaches are growing in importance. Market studies show that SiP devices will have an average growth of 10 to 20% per year over the next five years.

Ámbito científico (EuroSciVoc)

Programa(s)

Tema(s)

Convocatoria de propuestas

ENIAC-2009-1
Consulte otros proyectos de esta convocatoria

Régimen de financiación

JTI-CP-ENIAC - Joint Technology Initiatives - Collaborative Project (ENIAC)

Coordinador

INFINEON TECHNOLOGIES AG
Aportación de la UE
€ 634 152,00
Dirección
AM CAMPEON 1-15
85579 Neubiberg
Alemania
Región
Bayern Oberbayern München, Landkreis
Tipo de actividad
Private for-profit entities (excluding Higher or Secondary Education Establishments)
Enlaces
Coste total
Sin datos

Participantes (39)