Energy-efficient Heterogeneous COmputing at exaSCALE

Informazioni relative al progetto

ECOSCALE

ID dell’accordo di sovvenzione: 671632

DOI 10.3030/671632

Progetto chiuso

Data della firma CE 29 Giugno 2015

Data di avvio 1 Ottobre 2015

Data di completamento 31 Luglio 2019

Finanziato da

• EXCELLENT SCIENCE - Future and Emerging Technologies (FET)

Costo totale € 4 237 397,50

Contributo UE € 4 237 397,50

Coordinato da

EREVNITIKO PANEPISTIMIAKO INSTITOUTO TILEPIKONONIAKON SYSTIMATON
Greece

Risultati finali

Documents, reports (8)

Specifications of Systems Software and Programming Model

This deliverable will specify in detail the systems software that will unify different existing programming models as well as the programming environment that will take full advantage of the novel features of the ECOSCALE system.

Guidelines for efficiently programming ECOSCALE

Based on the porting of the beneficiaries' applications, this deliverable will provide guidelines for programming efficiently on the ECOSCALE platform.

Application analysis and system requirements

This deliverable will include the results from the analysis of the beneficiaries applications in terms of performance communication and power requirements Moreover based on this analysis this deliverable will report the essential system attributes and requirements that the ECOSCALEframework should provide

Specifications of Reconfigurable systems and Tools

This deliverable will specify in detail the specifications of the reconfigurable hardware system, of the software for implementing the reconfiguration features, as well as of the high-level hardware synthesis tool.

Evaluation of ECOSCALE platform

This deliverable will provide the report that describes the evaluation of the ECOSCALE platform using the applications of the beneficiaries.

Specs of Architecture and Prototype

This deliverable will identify the system components of the ECOSCALE architecture, their roles in the system and their interfaces. Moreover, it will provide the specifications of the ECOSCALE prototype.

Report on Co-design aspects

This deliverable will report the results from the monitoring, tuning and refinement of the co-design approach between the technical work packages and the applications development.

System integration and validation

This deliverable includes a report that describes the system-level integration and validation of the software and hardware components of the ECOSCALE platform.

Other (3)

Initial version, integrated tool flow

This deliverable will provide an integrated tool flow that will support the deployment of the hardware implementation of the kernels onto the platform developed in WP4. A report will also be provided as part of the deliverable.

Development UNIMEM + UNILOGIC architecture

This deliverbale will provide the reconfigurable design and implementation of the UNIMEM and UNILOGIC architecture. A report will also be provided as part of the deliverable.

Platform simulator

This deliverable will provide a scalable, abstract, yet precise enough simulation model that will be used to optimize various aspects and parameters of the architecture. A report will also be provided as part of the deliverable.

Websites, patent fillings, videos etc. (1)

Website

This deliverable includes the preparation and maintenance of the website.

Pubblicazioni

Peer reviewed articles (5)

Acceleration by Inline Cache for Memory-Intensive Algorithms on FPGA via High-Level Synthesis

Autori: Liang Ma, Luciano Lavagno, Mihai Teodor Lazarescu, Arslan Arif
Pubblicato in: IEEE Access, Numero 5, 2017, Pagina/e 18953-18974, ISSN 2169-3536
Editore: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/ACCESS.2017.2750923

Efficient FPGA Implementation of OpenCL High-Performance Computing Applications via High-Level Synthesis

Autori: Fahad Bin Muslim, Liang Ma, Mehdi Roozmeh, Luciano Lavagno
Pubblicato in: IEEE Access, Numero 5, 2017, Pagina/e 2747-2762, ISSN 2169-3536
Editore: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/ACCESS.2017.2671881

Performance and energy-efficient implementation of a smart city application on FPGAs

Autori: Arslan Arif, Felipe A. Barrigon, Francesco Gregoretti, Javed Iqbal, Luciano Lavagno, Mihai Teodor Lazarescu, Liang Ma, Manuel Palomino, Javier L. L. Segura
Pubblicato in: Journal of Real-Time Image Processing, 2018, ISSN 1861-8200
Editore: Springer Verlag
DOI: 10.1007/s11554-018-0792-x

DDRNoC

Autori: Ahsen Ejaz, Vassilios Papaefstathiou, Ioannis Sourdis
Pubblicato in: ACM Transactions on Architecture and Code Optimization, Numero 15/2, 2018, Pagina/e 1-24, ISSN 1544-3566
Editore: Association for Computing Machinary, Inc.
DOI: 10.1145/3200201

Decoupled Fused Cache

Autori: Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis
Pubblicato in: ACM Transactions on Architecture and Code Optimization, Numero 15/4, 2019, Pagina/e 1-23, ISSN 1544-3566
Editore: Association for Computing Machinary, Inc.
DOI: 10.1145/3293447

Conference proceedings (20)

A Scalable Runtime for the ECOSCALE Heterogeneous Exascale Hardware Platform

Autori: Paul Harvey, Konstantin Bakanov, Ivor Spence, Dimitrios S. Nikolopoulos
Pubblicato in: Proceedings of the 6th International Workshop on Runtime and Operating Systems for Supercomputers - ROSS '16, 2016, Pagina/e 1-8, ISBN 9781-450343879
Editore: ACM Press
DOI: 10.1145/2931088.2931090

ECOSCALE: Reconfigurable Computing and Runtime System for Future Exascale Systems

Autori: Mavroidis, Iakovos; Papaefstathiou, Ioannis; Lavagno, Luciano; Nikolopoulos, Dimitrios; Koch, Dirk; Goodacre, John; Sourdis, Ioannis; Papaefstathiou, Vassilis; Coppola, Marcello; Palomino, Manuel
Pubblicato in: Design, Automation & Test in Europe (DATE) 2016, 2016
Editore: IEEE
DOI: 10.5281/zenodo.34893

Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCL

Autori: Fahad Muslim, Alexandros Demian, Liang Ma, Luciano Lavagno, Affaq Qamar
Pubblicato in: Position Papers of the 2016 Federated Conference on Computer Science and Information Systems, 2016, Pagina/e 141-145, ISBN 978-83-60810-93-4
Editore: IEEE
DOI: 10.15439/2016F327

Implementation of a performance optimized database join operation on FPGA-GPU platforms using OpenCL

Autori: Mehdi Roozmeh, Luciano Lavagno
Pubblicato in: 2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2017, Pagina/e 1-6, ISBN 978-1-5386-2844-7
Editore: IEEE
DOI: 10.1109/NORCHIP.2017.8124981

High Performance and Low Power Monte Carlo Methods to Option Pricing Models via High Level Design and Synthesis

Autori: Liang Ma, Fahad Bin Muslim, Luciano Lavagno
Pubblicato in: 2016 European Modelling Symposium (EMS), 2016, Pagina/e 157-162, ISBN 978-1-5090-4971-4
Editore: IEEE
DOI: 10.1109/EMS.2016.036

Exact and Heuristic Allocation of Multi-kernel Applications to Multi-FPGA Platforms

Autori: Junnan Shan, Mario R. Casu, Jordi Cortadella, Luciano Lavagno, Mihai T. Lazarescu
Pubblicato in: Proceedings of the 56th Annual Design Automation Conference 2019 on - DAC '19, 2019, Pagina/e 1-6, ISBN 9781-450367257
Editore: ACM Press
DOI: 10.1145/3316781.3317821

FusionCache: Using LLC tags for DRAM cache

Autori: Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis
Pubblicato in: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, Pagina/e 593-596, ISBN 978-3-9819263-0-9
Editore: IEEE
DOI: 10.23919/date.2018.8342077

A Survey on FPGA Virtualization

Autori: Anuj Vaishnav, Khoa Dang Pham and Dirk Koch
Pubblicato in: 28th International Conference on Field Programmable Logic and Application (FPL), 2018
Editore: FPL

Resource Elastic Virtualization for FPGAs Using OpenCL

Autori: Anuj Vaishnav, Khoa Dang Pham, Dirk Koch, James Garside
Pubblicato in: 2018 28th International Conference on Field Programmable Logic and Applications (FPL), 2018, Pagina/e 111-1117, ISBN 978-1-5386-8517-4
Editore: IEEE
DOI: 10.1109/fpl.2018.00028

ZUCL: A ZYNQ UltraScale+ Framework for OpenCL HLS Applications

Autori: Khoa Pham, Anuj Vaishnav, Malte Vesper, Dirk Koch
Pubblicato in: FSP Workshop 2018; Fifth International Workshop on FPGAs for Software Programmers, Numero 31-31 Aug. 2018, 2018, ISBN 978-3-8007-4723-8
Editore: VDE

Live Migration for OpenCL FPGA Accelerators

Autori: Anuj Vaishnav, Khoa Pham, Dirk Koch
Pubblicato in: 2018 International Conference on Field-Programmable Technology (FPT), 2018, Pagina/e 38-45, ISBN 978-1-7281-0214-6
Editore: IEEE
DOI: 10.1109/fpt.2018.00017

IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs

Autori: Khoa Pham, Edson Horta, Dirk Koch, Anuj Vaishnav, Thomas Kuhn
Pubblicato in: 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2018, Pagina/e 36-43, ISBN 978-1-5386-6689-0
Editore: IEEE
DOI: 10.1109/mcsoc2018.2018.00018

FreewayNoC: A DDR NoC with Pipeline Bypassing

Autori: Ahsen Ejaz, Vassilios Papaefstathiou, Ioannis Sourdis
Pubblicato in: 2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2018, Pagina/e 1-8, ISBN 978-1-5386-4893-3
Editore: IEEE
DOI: 10.1109/nocs.2018.8512160

EFCAD — An Embedded FPGA CAD Tool Flow for Enabling On-chip Self-Compilation

Autori: Khoa Dang Pham, Malte Vesper, Dirk Koch, Eddie Hung
Pubblicato in: 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2019, Pagina/e 5-8, ISBN 978-1-7281-1131-5
Editore: IEEE
DOI: 10.1109/fccm.2019.00011

Heterogeneous Resource-Elastic Scheduling for CPU+FPGA Architectures

Autori: Anuj Vaishnav, Khoa Dang Pham, Dirk Koch
Pubblicato in: Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies - HEART 2019, 2019, Pagina/e 1-6, ISBN 9781-450372558
Editore: ACM Press
DOI: 10.1145/3337801.3337819

Scalable Filtering Modules for Database Acceleration on FPGAs

Autori: Kristiyan Manev, Anuj Vaishnav, Charalampos Kritikakis, Dirk Koch
Pubblicato in: Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies - HEART 2019, 2019, Pagina/e 1-6, ISBN 9781-450372558
Editore: ACM Press
DOI: 10.1145/3337801.3337810

LLC-Guided Data Migration in Hybrid Memory Systems

Autori: Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis
Pubblicato in: 2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2019, Pagina/e 932-942, ISBN 978-1-7281-1246-6
Editore: IEEE
DOI: 10.1109/ipdps.2019.00101

End-to-end Dynamic Stream Processing on Maxeler HLS Platforms

Autori: Charalampos Kritikakis, Dirk Koch
Pubblicato in: 2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2019, Pagina/e 59-66, ISBN 978-1-7281-1601-3
Editore: IEEE
DOI: 10.1109/asap.2019.00-29

BITMAN: A tool and API for FPGA bitstream manipulations

Autori: Khoa Dang Pham, Edson Horta, Dirk Koch
Pubblicato in: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, Pagina/e 894-897, ISBN 978-3-9815370-8-6
Editore: IEEE
DOI: 10.23919/date.2017.7927114

Accelerating Linux Bash Commands on FPGAs Using Partial Reconfiguration

Autori: Edson Horta, Xinzi Shen, Khoa Pham, Dirk Koch
Pubblicato in: FPGAs for Software Programmers (FSP), 2017, 2017, ISBN 978-3-8007-4443-5
Editore: IEEE

Thesis and dissertations (2)

DDRNoC: Dual Data-Rate Network-on-Chip

Autori: Ejaz, Ahsen
Pubblicato in: 2018
Editore: Chalmers

Runtime Management of Multiprocessor Systems for Fault Tolerance, Energy Efficiency and Load Balancing

Autori: Tzilis, Stavros
Pubblicato in: 2019
Editore: Chalmers

Book chapters (4)

HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware - ECOSCALE

Autori: Pavlos Malakonakis, Konstantinos Georgopoulos, Aggelos Ioannou, Luciano Lavagno, Ioannis Papaefstathiou, Iakovos Mavroidis
Pubblicato in: Applied Reconfigurable Computing. Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings, Numero 10824, 2018, Pagina/e 724-736, ISBN 978-3-319-78889-0
Editore: Springer International Publishing
DOI: 10.1007/978-3-319-78890-6_58

HLS Enabled Partially Reconfigurable Module Implementation

Autori: Nicolae Bogdan Grigore, Charalampos Kritikakis, Dirk Koch
Pubblicato in: Architecture of Computing Systems – ARCS 2018, Numero 10793, 2018, Pagina/e 269-282, ISBN 978-3-319-77609-5
Editore: Springer International Publishing
DOI: 10.1007/978-3-319-77610-1_20

Energy-Efficient Heterogeneous Computing at exaSCALE—ECOSCALE

Autori: Konstantinos Georgopoulos, Iakovos Mavroidis, Luciano Lavagno, Ioannis Papaefstathiou, Konstantin Bakanov
Pubblicato in: Hardware Accelerators in Data Centers, 2019, Pagina/e 199-213, ISBN 978-3-319-92791-6
Editore: Springer International Publishing
DOI: 10.1007/978-3-319-92792-3_11

A Novel Framework for Utilising Multi-FPGAs in HPC Systems

Autori: K. Georgopoulos, K. Bakanov, I. Mavroidis, I. Papaefstathiou, A. Ioannou, P. Malakonakis, K. Pham, D. Koch, L. Lavagno
Pubblicato in: Heterogeneous Computing Architectures - Challenges and Vision, 2019, Pagina/e 153-189, ISBN 9780-429399602
Editore: CRC Press
DOI: 10.1201/9780429399602-7

Other (1)

EU Projects Unite on Heterogeneous ARM-based Exascale Prototype

Autori: Tiffany Trader
Pubblicato in: HPCWire, Numero February 24, 2016, 2016
Editore: HPCWire