Validation of European high capacity rad-hard FPGA and software tools

Información del proyecto

VEGAS

Identificador del acuerdo de subvención: 687220

DOI

10.3030/687220

Proyecto cerrado

Fecha de la firma de la CE 23 Noviembre 2015

Fecha de inicio 1 Enero 2016

Fecha de finalización 31 Agosto 2020

Financiado con arreglo a

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies – Space

Coste total

€ 3 976 861,25

Aportación de la UE

€ 3 975 311,25

Coordinado por

NANOXPLORE
France

CORDIS proporciona enlaces a los documentos públicos y las publicaciones de los proyectos de los programas marco HORIZONTE.

Los enlaces a los documentos y las publicaciones de los proyectos del Séptimo Programa Marco, así como los enlaces a algunos tipos de resultados específicos, como conjuntos de datos y «software», se obtienen dinámicamente de OpenAIRE .

Resultado final

Documents, reports (28)

Periodic progress report 1
Report on fault injection

Report on fault injection Static analysis evaluation of SEE and MCU sensitiveness Check the robustness of the FPGA by implementing a critical design, adding the new SEE monitoring function and checking them by injecting errors at HW level Analysis and recommendation of the FPGA behavior concerning in-flight usage Analyze fault injection experiments contrasted with radiation effects experiments over the same circuits

AGGA4 Portability Performance Report

GNSS receiver IP portability assessment: Revision and optimization of VHDL code to match the target FPGAs and use their specific HW resources VHDL simulations to assess the integrity of the design after VHDL rework Synthesis, Place and Route the design for the target FPGAs Timing, integration and electrical performances measurement on Evaluation Board for critical functions Performance analysis, speed, area, consumption, comparison with other FPGA technologies Generate the relevant reports

Commercialization exploitation report
Data package DELTA ESCC Evaluation

Results on ESSC delta to QML-V qualification flow

IFFT Radix 2 and Radix 4 and Digital Down Converter (DDC) portability study

IFFT Radix 2 and Radix 4 and Digital Down Converter (DDC) portability study Revision and optimization of VHDL code to match the target FPGAs and use their specific HW resources VHDL simulations to assess the integrity of the design after VHDL rework Synthesis, Place and Route the design for the target FPGAs Timing, integration and electrical performances measurement on Evaluation Board for critical functions Performance analysis, speed, area, consumption, comparison with other FPGA technologies Generate the relevant reports

Benchmark analysis for SEU mitigation driven designs

Benchmark radiative tests results using Veri-Place features.

Identification of tasks and deliverables leaders report
SpW/FPU/Motor CTL Portability Performance Report

SpW/FPU/Motor CTL Portability Performance Report Revision and optimization of VHDL code to match the target FPGAs and use their specific HW resources VHDL simulations to assess the integrity of the design after VHDL rework Synthesis, Place and Route the design for the target FPGAs Timing, integration and electrical performances measurement on Evaluation Board for critical functions Performance analysis, speed, area, consumption, comparison with other FPGA technologies Generate the relevant reports

Systematic FPGA Functions Validation Report

Report on FPGA functional testing by end-user post IP portability assessment

Final dissemination and exploitation report
CGA625 Assembly Validation Plan

CGA625 Assembly Validation Plan Phase 1 Manufacturing capability: PCB design, Manufacturing activities according to the agreed plan; 2 CGA625 soldering, desoldering, Qualification campaign; vibration and 500 cycles, Verification; micro sections, PCB integrity

Periodic progress report 2
Data package QML-V lot 1 qualification CQFP 352

results on QML-V lot 1 qualification flow

Periodic progress report 3

Final report

Report of the test vehicles useable for a radiation test using University of Sevilla facilities. Simulate the possible effects over the target technology.

Report of the test vehicles useable for a radiation test using University of Sevilla facilities. Simulate the possible effects over the target technology.

Dissemination and exploitation progress reports 2
CGA625 Assembly Reliability Report

CGA625 Assembly Reliability Report Phase 2 Verification program: PCB design, Manufacturing activities according to the agreed plan; 4 CGA625 soldering, desoldering, Qualification campaign; vibration and 1500 cycles with electrical monitoring The tests are done with normal CGA 625 FPGA and not daisy chain.

Final report

Final report covering the full VEGAs activities and results achieved

Dual use report 2
Dual use report 1
Perform and reporting of radiation tests

Do the radiative tests and write results report

FPGA Portability, Performance and Package Assembly Summary report

FPGA Portability, Performance and Package Assembly Summary report Final report on FPGA performance and reliability

Analyze the obtained results

Analyze results on fault injection + radiative test

Dissemination and exploitation plan presentation
Data package characterization report

Report on full characterisation under QML-V flow

Report on developed IPs

IPs to be developped for NanoXmap software DSP integration with high level tools (SimuLink) DDR3 Dual clock FIFO

Dissemination and exploitation progress reports 1

Demonstrators, pilots, prototypes (2)

An operative platform adapted to the FPGA for Fault Injection

Development of an operative platform adapted to the FPGA for Fault Injection.

An operative platform suitable for radiation testing of the Brave FPGA

Final operative platform adapted to BRAVE FPGA

Publicaciones

Peer reviewed articles (3)

SW-VHDL Co-Verification Environment Using Open Source Tools

Autores: Maria Muñoz-Quijada, Luis Sanz, Hipolito Guzman-Miranda
Publicado en: Electronics, Edición 9/12, 2020, Página(s) 2104, ISSN 2079-9292
Editor: Electronics (MDPI)
DOI: 10.3390/electronics9122104

Fine-Grain Circuit Hardening Through VHDL Datatype Substitution

Autores: Maria Muñoz-Quijada, Samuel Sanchez-Barea, Daniel Vela-Calderon, Hipolito Guzman-Miranda
Publicado en: Electronics, Edición 8/1, 2019, Página(s) 24, ISSN 2079-9292
Editor: Electronics (MDPI)
DOI: 10.3390/electronics8010024

A Virtual Device for Simulation-Based Fault Injection

Autores: Maria Muñoz-Quijada, Luis Sanz, Hipolito Guzman-Miranda
Publicado en: Electronics, Edición 9/12, 2020, Página(s) 1989, ISSN 2079-9292
Editor: Electronics (MDPI)
DOI: 10.3390/electronics9121989

Book chapters (1)

Fine-Grain Circuit Hardening Through VHDL Datatype Substitution

Autores: Maria Muñoz-Quijada, Samuel Sanchez-Barea, Daniel Vela-Calderon and Hipolito Guzman-Miranda
Publicado en: Radiation Tolerant Electronics, 2019
Editor: Paul Leroux

Conference proceedings (2)

Harsher-than-space: Fault injection and user-based RHBD in the age of rad-tolerant and rad-hard devices

Autores: Hipólito Guzmán-Miranda, María Muñoz-Quijada, José R. García-Oya, Jorge Jiménez-Sánchez, Luis Sanz, Fernando Márquez-Lasso, Fernando Muñoz
Publicado en: 5th SEFUW (SpacE FPGA Users Workshop), 2020
Editor: ESA

Fault injection for space: FT-Unshades2 updates, experiences and roadmap

Autores: Hipólito Guzmán-Miranda, María Muñoz-Quijada, Luis Sanz
Publicado en: 4th SEFUW (SpacE FPGA Users Workshop), 2018
Editor: ESA