Validation of European high capacity rad-hard FPGA and software tools

Informazioni relative al progetto

VEGAS

ID dell’accordo di sovvenzione: 687220

DOI

10.3030/687220

Progetto chiuso

Data della firma CE 23 Novembre 2015

Data di avvio 1 Gennaio 2016

Data di completamento 31 Agosto 2020

Finanziato da

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies – Space

Costo totale

€ 3 976 861,25

Contributo UE

€ 3 975 311,25

Coordinato da

NANOXPLORE
France

CORDIS fornisce collegamenti ai risultati finali pubblici e alle pubblicazioni dei progetti ORIZZONTE.

I link ai risultati e alle pubblicazioni dei progetti del 7° PQ, così come i link ad alcuni tipi di risultati specifici come dataset e software, sono recuperati dinamicamente da .OpenAIRE .

Risultati finali

Documents, reports (28)

Periodic progress report 1
Report on fault injection

Report on fault injection Static analysis evaluation of SEE and MCU sensitiveness Check the robustness of the FPGA by implementing a critical design, adding the new SEE monitoring function and checking them by injecting errors at HW level Analysis and recommendation of the FPGA behavior concerning in-flight usage Analyze fault injection experiments contrasted with radiation effects experiments over the same circuits

AGGA4 Portability Performance Report

GNSS receiver IP portability assessment: Revision and optimization of VHDL code to match the target FPGAs and use their specific HW resources VHDL simulations to assess the integrity of the design after VHDL rework Synthesis, Place and Route the design for the target FPGAs Timing, integration and electrical performances measurement on Evaluation Board for critical functions Performance analysis, speed, area, consumption, comparison with other FPGA technologies Generate the relevant reports

Commercialization exploitation report
Data package DELTA ESCC Evaluation

Results on ESSC delta to QML-V qualification flow

IFFT Radix 2 and Radix 4 and Digital Down Converter (DDC) portability study

IFFT Radix 2 and Radix 4 and Digital Down Converter (DDC) portability study Revision and optimization of VHDL code to match the target FPGAs and use their specific HW resources VHDL simulations to assess the integrity of the design after VHDL rework Synthesis, Place and Route the design for the target FPGAs Timing, integration and electrical performances measurement on Evaluation Board for critical functions Performance analysis, speed, area, consumption, comparison with other FPGA technologies Generate the relevant reports

Benchmark analysis for SEU mitigation driven designs

Benchmark radiative tests results using Veri-Place features.

Identification of tasks and deliverables leaders report
SpW/FPU/Motor CTL Portability Performance Report

SpW/FPU/Motor CTL Portability Performance Report Revision and optimization of VHDL code to match the target FPGAs and use their specific HW resources VHDL simulations to assess the integrity of the design after VHDL rework Synthesis, Place and Route the design for the target FPGAs Timing, integration and electrical performances measurement on Evaluation Board for critical functions Performance analysis, speed, area, consumption, comparison with other FPGA technologies Generate the relevant reports

Systematic FPGA Functions Validation Report

Report on FPGA functional testing by end-user post IP portability assessment

Final dissemination and exploitation report
CGA625 Assembly Validation Plan

CGA625 Assembly Validation Plan Phase 1 Manufacturing capability: PCB design, Manufacturing activities according to the agreed plan; 2 CGA625 soldering, desoldering, Qualification campaign; vibration and 500 cycles, Verification; micro sections, PCB integrity

Periodic progress report 2
Data package QML-V lot 1 qualification CQFP 352

results on QML-V lot 1 qualification flow

Periodic progress report 3

Final report

Report of the test vehicles useable for a radiation test using University of Sevilla facilities. Simulate the possible effects over the target technology.

Report of the test vehicles useable for a radiation test using University of Sevilla facilities. Simulate the possible effects over the target technology.

Dissemination and exploitation progress reports 2
CGA625 Assembly Reliability Report

CGA625 Assembly Reliability Report Phase 2 Verification program: PCB design, Manufacturing activities according to the agreed plan; 4 CGA625 soldering, desoldering, Qualification campaign; vibration and 1500 cycles with electrical monitoring The tests are done with normal CGA 625 FPGA and not daisy chain.

Final report

Final report covering the full VEGAs activities and results achieved

Dual use report 2
Dual use report 1
Perform and reporting of radiation tests

Do the radiative tests and write results report

FPGA Portability, Performance and Package Assembly Summary report

FPGA Portability, Performance and Package Assembly Summary report Final report on FPGA performance and reliability

Analyze the obtained results

Analyze results on fault injection + radiative test

Dissemination and exploitation plan presentation
Data package characterization report

Report on full characterisation under QML-V flow

Report on developed IPs

IPs to be developped for NanoXmap software DSP integration with high level tools (SimuLink) DDR3 Dual clock FIFO

Dissemination and exploitation progress reports 1

Demonstrators, pilots, prototypes (2)

An operative platform adapted to the FPGA for Fault Injection

Development of an operative platform adapted to the FPGA for Fault Injection.

An operative platform suitable for radiation testing of the Brave FPGA

Final operative platform adapted to BRAVE FPGA

Pubblicazioni

Peer reviewed articles (3)

SW-VHDL Co-Verification Environment Using Open Source Tools

Autori: Maria Muñoz-Quijada, Luis Sanz, Hipolito Guzman-Miranda
Pubblicato in: Electronics, Numero 9/12, 2020, Pagina/e 2104, ISSN 2079-9292
Editore: Electronics (MDPI)
DOI: 10.3390/electronics9122104

Fine-Grain Circuit Hardening Through VHDL Datatype Substitution

Autori: Maria Muñoz-Quijada, Samuel Sanchez-Barea, Daniel Vela-Calderon, Hipolito Guzman-Miranda
Pubblicato in: Electronics, Numero 8/1, 2019, Pagina/e 24, ISSN 2079-9292
Editore: Electronics (MDPI)
DOI: 10.3390/electronics8010024

A Virtual Device for Simulation-Based Fault Injection

Autori: Maria Muñoz-Quijada, Luis Sanz, Hipolito Guzman-Miranda
Pubblicato in: Electronics, Numero 9/12, 2020, Pagina/e 1989, ISSN 2079-9292
Editore: Electronics (MDPI)
DOI: 10.3390/electronics9121989

Book chapters (1)

Fine-Grain Circuit Hardening Through VHDL Datatype Substitution

Autori: Maria Muñoz-Quijada, Samuel Sanchez-Barea, Daniel Vela-Calderon and Hipolito Guzman-Miranda
Pubblicato in: Radiation Tolerant Electronics, 2019
Editore: Paul Leroux

Conference proceedings (2)

Harsher-than-space: Fault injection and user-based RHBD in the age of rad-tolerant and rad-hard devices

Autori: Hipólito Guzmán-Miranda, María Muñoz-Quijada, José R. García-Oya, Jorge Jiménez-Sánchez, Luis Sanz, Fernando Márquez-Lasso, Fernando Muñoz
Pubblicato in: 5th SEFUW (SpacE FPGA Users Workshop), 2020
Editore: ESA

Fault injection for space: FT-Unshades2 updates, experiences and roadmap

Autori: Hipólito Guzmán-Miranda, María Muñoz-Quijada, Luis Sanz
Pubblicato in: 4th SEFUW (SpacE FPGA Users Workshop), 2018
Editore: ESA