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Twinning to Strengthen Tallinn University of Technology’s Research and Innovation Capacity in Nanoelectronics Based Dependable Cyber-Physical Systems

Deliverables

Project newsletters

1-2 newsletters/year over the duration of the project.

Promotion guide about TUT

Promotion guide about TUT.

Project website

Project website

Project leaflet and poster

• Project leaflet (2 pages, A4 size) and Powerpoint presentation providing overview of the project • Project poster (A1 size)

Publications

Designing Reliable Cyber-Physical Systems

Author(s): Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Goerschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Shlomit Koyfman, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
Published in: Lecture Notes in Electrical Engineering, 2018, Page(s) 15-38
DOI: 10.1007/978-3-319-62920-9_2

A Study on Immediate Automatic Usability Evaluation of Web Application User Interfaces

Author(s): Jevgeni Marenkov, Tarmo Robal, Ahto Kalja
Published in: Databases and Information Systems, Issue 615, 2016, Page(s) 257-271
DOI: 10.1007/978-3-319-40180-5_18

A Tool for Design-Time Usability Evaluation of Web User Interfaces

Author(s): Jevgeni Marenkov, Tarmo Robal, Ahto Kalja
Published in: Advances in Databases and Information Systems, Issue 10509, 2017, Page(s) 394-407
DOI: 10.1007/978-3-319-66917-5_26

Can I Have a Mooc2Go, Please? On the Viability of Mobile vs. Stationary Learning

Author(s): Yue Zhao, Tarmo Robal, Christoph Lofi, Claudia Hauff
Published in: Lifelong Technology-Enhanced Learning - 13th European Conference on Technology Enhanced Learning, EC-TEL 2018, Leeds, UK, September 3-5, 2018, Proceedings, Issue 11082, 2018, Page(s) 101-115
DOI: 10.1007/978-3-319-98572-5_8

Classification Algorithm Improvement for Physical Activity Recognition in Maritime Environments

Author(s): Ardo Allik, Kristjan Pilt, Deniss Karai, Ivo Fridolin, Mairo Leier, Gert Jervan
Published in: World Congress on Medical Physics and Biomedical Engineering 2018, Issue 68/3, 2019, Page(s) 13-17
DOI: 10.1007/978-981-10-9023-3_3

EEG Functional Connectivity Detects Seasonal Changes

Author(s): Laura Päeske, Maie Bachmann, Jaan Raik, Hiie Hinrikus
Published in: World Congress on Medical Physics and Biomedical Engineering 2018 - June 3-8, 2018, Prague, Czech Republic (Vol.2), Issue 68/2, 2019, Page(s) 237-240
DOI: 10.1007/978-981-10-9038-7_44

Energy-Efficient Multi-fragment Markov Model Guided Online Model-Based Testing for MPSoC

Author(s): Jüri Vain, Leonidas Tsiopoulos, Vyacheslav Kharchenko, Apneet Kaur, Maksim Jenihhin, Jaan Raik, Sven Nõmm
Published in: Green IT Engineering: Social, Business and Industrial Applications, Issue 171, 2019, Page(s) 273-297
DOI: 10.1007/978-3-030-00253-4_12

Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs

Author(s): Raimund Ubar, Lembit Jürimägi, Elmet Orasson, Jaan Raik
Published in: VLSI-SoC: Design for Reliability, Security, and Low Power, Issue 483, 2016, Page(s) 23-45
DOI: 10.1007/978-3-319-46097-0_2

Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation

Author(s): Marco Gaudesi, Maksim Jenihhin, Jaan Raik, Ernesto Sanchez, Giovanni Squillero, Valentin Tihhomirov, Raimund Ubar
Published in: Applications of Evolutionary Computation, 2014, Page(s) 425-436
DOI: 10.1007/978-3-662-45523-4_35

Fast identification of true critical paths in sequential circuits

Author(s): Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Lembit Jürimägi
Published in: Microelectronics Reliability, Issue 81, 2018, Page(s) 252-261, ISSN 0026-2714
DOI: 10.1016/j.microrel.2017.11.027

Modeling and simulation of circuits with shared structurally synthesized BDDs

Author(s): Raimund Ubar, Lembit Jürimägi, Jaan Raik, Vladimir Viies
Published in: Microprocessors and Microsystems, Issue 48, 2017, Page(s) 56-61, ISSN 0141-9331
DOI: 10.1016/j.micpro.2016.09.006

Health Management for Self-Aware SoCs Based on IEEE 1687 Infrastructure


Published in: ISSN 2168-2356
DOI: 10.1109/MDAT.2017.2750902

Run-time reconfigurable instruments for advanced board-level testing


Published in: ISSN 1094-6969
DOI: 10.1109/MIM.2017.8006390

Fast Data Sort based on Searching Networks with Ring Pipeline

Author(s): Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson
Published in: Elektronika ir Elektrotechnika, Issue 22/4, 2016, ISSN 1392-1215
DOI: 10.5755/j01.eie.22.4.15920

Fast iterative circuits and RAM-based mergers to accelerate data sort in software/hardware systems

Author(s): V Sklyarov, I Skliarova, A Rjabov, A Sudnitson
Published in: Proceedings of the Estonian Academy of Sciences, Issue 66/3, 2017, Page(s) 323, ISSN 1736-6046
DOI: 10.3176/proc.2017.3.07

Guest Editorial: Implementation Issues in System-on-Chip

Author(s): Peeter Ellervee, Jari Nurmi
Published in: Journal of Signal Processing Systems, Issue 87/3, 2017, Page(s) 269-270, ISSN 1939-8018
DOI: 10.1007/s11265-017-1242-x

Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures

Author(s): Igor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin
Published in: Journal of Electronic Testing, Issue 32/3, 2016, Page(s) 245-255, ISSN 0923-8174
DOI: 10.1007/s10836-016-5588-y

Polymorphic Configuration Architecture for CGRAs

Author(s): Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Ahmed Hemani, Kolin Paul, Juha Plosila, Peeter Ellervee, Hannu Tenuhnen
Published in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Issue 24/1, 2016, Page(s) 403-407, ISSN 1063-8210
DOI: 10.1109/tvlsi.2015.2402392

Surrogate Data Method Requires End-Matched Segmentation of Electroencephalographic Signals to Estimate Non-linearity

Author(s): Laura Päeske, Maie Bachmann, Toomas Põld, Sara Pereira Mendes de Oliveira, Jaanus Lass, Jaan Raik, Hiie Hinrikus
Published in: Frontiers in Physiology, Issue 9, 2018, ISSN 1664-042X
DOI: 10.3389/fphys.2018.01350

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

Author(s): Maksim Jenihhin, Giovanni Squillero, Thiago Santos Copetti, Valentin Tihhomirov, Sergei Kostin, Marco Gaudesi, Fabian Vargas, Jaan Raik, Matteo Sonza Reorda, Leticia Bolzani Poehls, Raimund Ubar, Guilherme Cardoso Medeiros
Published in: Journal of Electronic Testing, Issue 32/3, 2016, Page(s) 273-289, ISSN 0923-8174
DOI: 10.1007/s10836-016-5589-x

Functional self-test of high-performance pipe-lined signal processing architectures

Author(s): Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min
Published in: Microprocessors and Microsystems, Issue 39/8, 2015, Page(s) 909-918, ISSN 0141-9331
DOI: 10.1016/j.micpro.2014.11.002

Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra

Author(s): Jaak Kõusaar, Raimund Ubar, Sergei Devadze, Jaan Raik
Published in: Microprocessors and Microsystems, Issue 39/8, 2015, Page(s) 1130-1138, ISSN 0141-9331
DOI: 10.1016/j.micpro.2015.05.003

Automated Design Error Localization in RTL Designs


Published in: ISSN 2168-2356
DOI: 10.1109/MDAT.2013.2271420

Automated design error debug using high-level decision diagrams and mutation operators

Author(s): Jaan Raik, Urmas Repinski, Anton Chepurov, Hanno Hantson, Raimund Ubar, Maksim Jenihhin
Published in: Microprocessors and Microsystems, Issue 37/4-5, 2013, Page(s) 505-513, ISSN 0141-9331
DOI: 10.1016/j.micpro.2012.11.004

Comprehensive performance and robustness analysis of 2D turn models for network-on-chips

Author(s): Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Thilo Kogge, Jaan Raik, Gert Jervan, Thomas Hollstein
Published in: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, Page(s) 1-4
DOI: 10.1109/ISCAS.2017.8050634

High-level test generation for processing elements in many-core systems

Author(s): Adeboye Stephen Oyeniran, Raimund Ubar, Siavoosh Payandeh Azad, Jaan Raik
Published in: 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, Page(s) 1-8
DOI: 10.1109/ReCoSoC.2017.8016156

Fault-resilient NoC router with transparent resource allocation

Author(s): Tsotne Putkaradze, Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik, Gert Jervan
Published in: 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, Page(s) 1-8
DOI: 10.1109/ReCoSoC.2017.8016161

Automated area and coverage optimization of minimal latency checkers

Author(s): Siavoosh Payandeh Azad, Behrad Niazmand, Apneet Kaur Sandhu, Jaan Raik, Gert Jervan, Thomas Hollstein
Published in: 2017 22nd IEEE European Test Symposium (ETS), 2017, Page(s) 1-2
DOI: 10.1109/ETS.2017.7968211

Marginal PCB assembly defect detection on DDR3/4 memory bus

Author(s): Sergei Odintsov, Artur Jutman, Sergei Devadze
Published in: 2017 IEEE International Test Conference (ITC), 2017, Page(s) 1-10
DOI: 10.1109/TEST.2017.8242070

Embedded instrumentation toolbox for screening marginal defects and outliers for production

Author(s): Sergei Odintsov, Artur Jutman, Sergei Devadze, Igor Aleksejev
Published in: 2017 IEEE AUTOTESTCON, 2017, Page(s) 1-9
DOI: 10.1109/AUTEST.2017.8080516

Multi-view modeling for MPSoC design aspects

Author(s): Juri Vain, Apneet Kaur, Leonidas Tsiopoulos, Jaan Raik, Maksim Jenihhin
Published in: 2018 16th Biennial Baltic Electronics Conference (BEC), 2018, Page(s) 1-6
DOI: 10.1109/bec.2018.8600986

A Hierarchical Approach for Devising Area Efficient Concurrent Online Checkers

Author(s): Behrad Niazmand, Siavoosh Payandeh Azad, Tara Ghasempouri, Jaan Raik, Gert Jervan
Published in: 2018 IEEE International Test Conference in Asia (ITC-Asia), 2018, Page(s) 139-144
DOI: 10.1109/itc-asia.2018.00034

A novel random approach to diagnostic test generation

Author(s): Emmanuel Ovie Osimiry, Raimund Ubar, Sergei Kostin, Jaan Raik
Published in: 2016 IEEE Nordic Circuits and Systems Conference (NORCAS), 2016, Page(s) 1-4
DOI: 10.1109/norchip.2016.7792915

A suite of IEEE 1687 benchmark networks

Author(s): Anton Tsertov, Artur Jutman, Sergei Devadze, Matteo Sonza Reorda, Erik Larsson, Farrokh Ghani Zadegan, Riccardo Cantoro, Mehrdad Montazeri, Rene Krenz-Baath
Published in: 2016 IEEE International Test Conference (ITC), 2016, Page(s) 1-10
DOI: 10.1109/test.2016.7805840

A tool for random test generation targeting high diagnostic resolution

Author(s): Emmanuel Ovie Osimiry, Sergei Kostin, Jaan Raik, Raimund Ubar
Published in: 2016 15th Biennial Baltic Electronics Conference (BEC), 2016, Page(s) 79-82
DOI: 10.1109/bec.2016.7743733

A tool set for teaching design-for-testability of digital circuits

Author(s): S. Kostin, E. Orasson, R. Ubar
Published in: 2016 11th European Workshop on Microelectronics Education (EWME), 2016, Page(s) 1-6
DOI: 10.1109/ewme.2016.7496466

Activity classification for real-time wearable systems: Effect of window length, sampling frequency and number of features on classifier performance

Author(s): Ardo Allik, Kristjan Pilt, Deniss Karai, Ivo Fridolin, Mairo Leier, Gert Jervan
Published in: 2016 IEEE EMBS Conference on Biomedical Engineering and Sciences (IECBES), 2016, Page(s) 460-464
DOI: 10.1109/iecbes.2016.7843493

Administration of the State Information System of the Estonian eGovernment

Author(s): Ahto Kalja, Tarmo Robal, Triin Gailan
Published in: 2017 Portland International Conference on Management of Engineering and Technology (PICMET), 2017, Page(s) 1-7
DOI: 10.23919/picmet.2017.8125312

An Automatic Approach to Evaluate Assertions' Quality Based on Data-Mining Metrics

Author(s): Tara Ghasempouri, Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik
Published in: 2018 IEEE International Test Conference in Asia (ITC-Asia), 2018, Page(s) 61-66
DOI: 10.1109/itc-asia.2018.00021

AWAIT: An Ultra-Lightweight Soft-Error Mitigation Mechanism for Network-on-Chip Links

Author(s): Karl Janson, Rene Pihlak, Siavoosh Payandeh Azad, Behrad Niazmand, Gert Jervan, Jaan Raik
Published in: 2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2018, Page(s) 1-6
DOI: 10.1109/recosoc.2018.8449374

Augmented Coaching Ecosystem for Non-obtrusive Adaptive Personalized Elderly Care on the basis of Cloud-Fog-Dew computing paradigm

Author(s): Yu. Gordienko, S. Stirenko, O. Alienin, K. Skala, Z. Sojat, A. Rojbi, J.R. Lopez Benito, E. Artetxe Gonzalez, U. Lushchyk, L. Sajn, A. Llorente Coto, G. Jervan
Published in: 2017 40th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO), 2017, Page(s) 359-364
DOI: 10.23919/mipro.2017.7973449

Combined pseudo-exhaustive and deterministic testing of array multipliers

Author(s): Adeboye Stephen Oyeniran, Siavoosh Payandeh Azad, Raimund Ubar
Published in: 2018 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR), 2018, Page(s) 1-6
DOI: 10.1109/aqtr.2018.8402708

Data type dependent energy consumption estimation

Author(s): Priit Ruberg, Keijo Lass, Peeter Ellervee
Published in: 2016 IEEE Nordic Circuits and Systems Conference (NORCAS), 2016, Page(s) 1-5
DOI: 10.1109/norchip.2016.7792916

Developing a data acquisition system for measuring microcontroller energy consumption using LabVIEW

Author(s): Priit Ruberg, Keijo Lass, Peeter Ellervee
Published in: 2016 15th Biennial Baltic Electronics Conference (BEC), 2016, Page(s) 123-126
DOI: 10.1109/bec.2016.7743744

Embedded software performance estimations at different compiler optimisation levels

Author(s): Priit Ruberg, Keijo Lass, Elvar Liiv, Peeter Ellervee
Published in: 2017 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE), 2017, Page(s) 1-6
DOI: 10.1109/aieee.2017.8270530

Parallel Critical Path Tracing Fault Simulation in Sequential Circuits

Author(s): Jaak Kousaar, Raimund Ubar, Sergei Kostin, Sergei Devadze, Jaan Raik
Published in: "2018 25th International Conference ""Mixed Design of Integrated Circuits and System"" (MIXDES)", 2018, Page(s) 305-310
DOI: 10.23919/mixdes.2018.8436880

Fair and Individualized Project Teamwork Evaluation for an Engineering Course

Author(s): Tarmo Robal
Published in: 2018 28th EAEEIE Annual Conference (EAEEIE), 2018, Page(s) 1-9
DOI: 10.1109/eaeeie.2018.8534256

Fall detection and activity recognition system for usage in smart work-wear

Author(s): Mairo Leier, Gert Jervan, Ardo Allik, Kristjan Pilt, Deniss Karai, Ivo Fridolin
Published in: 2018 16th Biennial Baltic Electronics Conference (BEC), 2018, Page(s) 1-4
DOI: 10.1109/bec.2018.8600959

Conditional Fault Collapsing in Digital Circuits with Shared Structurally Synthesized BDDs

Author(s): Lembit Jurimagi, Raimund Ubar
Published in: 2018 16th Biennial Baltic Electronics Conference (BEC), 2018, Page(s) 1-4
DOI: 10.1109/bec.2018.8600967

Gate-level modelling of NBTI-induced delays under process variations

Author(s): Thiago Copetti, Guilherme Medeiros, Leticia Bolzani Poehls, Fabian Vargas, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Raimund Ubar
Published in: 2016 17th Latin-American Test Symposium (LATS), 2016, Page(s) 75-80
DOI: 10.1109/latw.2016.7483343

Guideliner - a Tool to Improve Web UI Development for Better Usability

Author(s): Jevgeni Marenkov, Tarmo Robal, Ahto Kalja
Published in: Proceedings of the 8th International Conference on Web Intelligence, Mining and Semantics - WIMS '18, 2018, Page(s) 1-9
DOI: 10.1145/3227609.3227667

Handling of SETs on NoC Links by Exploitation of Inherent Redundancy in Circular Input Buffers

Author(s): Karl Janson, Rene Pihlak, Siavoosh Payandeh Azad, Behrad Niazmand, Gert Jervan, Jaan Raik
Published in: 2018 16th Biennial Baltic Electronics Conference (BEC), 2018, Page(s) 1-4
DOI: 10.1109/bec.2018.8600989

Hardware implementation of face recognition using low precision representation

Author(s): Sai Kumar Dwivedi, Siavoosh Payandeh Azad, Peeter Ellervee, Ratnakar Dash
Published in: 2016 15th Biennial Baltic Electronics Conference (BEC), 2016, Page(s) 63-66
DOI: 10.1109/bec.2016.7743729

Hardware-based systems for partial sorting of streaming data

Author(s): Artjom Rjabov
Published in: 2016 15th Biennial Baltic Electronics Conference (BEC), 2016, Page(s) 59-62
DOI: 10.1109/bec.2016.7743728

Hierarchical Timing-Critical Paths Analysis in Sequential Circuits

Author(s): Lembit Jurimagi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Sergei Kostin
Published in: 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2018, Page(s) 1-6
DOI: 10.1109/patmos.2018.8464176

High-level test data generation for software-based self-test in microprocessors

Author(s): Adeboye Stephen Oyeniran, Artjom Jasnetski, Anton Tsertov, Raimund Ubar
Published in: 2017 6th Mediterranean Conference on Embedded Computing (MECO), 2017, Page(s) 1-6
DOI: 10.1109/meco.2017.7977167

IEEE 1687 Compliant Ecosystem for Embedded Instrumentation Access and In-Field Health Monitoring

Author(s): Anton Tsertov, Artur Jutman, Konstantin Shibin, Sergei Devadze
Published in: 2018 IEEE AUTOTESTCON, 2018, Page(s) 1-9
DOI: 10.1109/autest.2018.8532559

In-Field Detection of Degradation on PCB Assembly High-Speed Buses

Author(s): Sergei Odintsov
Published in: 2018 IEEE AUTOTESTCON, 2018, Page(s) 1-6
DOI: 10.1109/autest.2018.8532547

Understanding MPSoCs - exploiting memory microarchitectural vulnerabilities of high performance NoC-based MPSoCs

Author(s): Johanna Sepulveda, Cezar Reinbrecht, Siavoosh Payandeh Azad, Behrad Niazmand, Gert Jervan
Published in: Proceedings of the 18th International Conference on Embedded Computer Systems Architectures, Modeling, and Simulation - SAMOS '18, 2018, Page(s) 162-166
DOI: 10.1145/3229631.3239367

IntelliEye - Enhancing MOOC Learners' Video Watching Experience through Real-Time Attention Tracking

Author(s): Tarmo Robal, Yue Zhao, Christoph Lofi, Claudia Hauff
Published in: Proceedings of the 29th on Hypertext and Social Media - HT '18, 2018, Page(s) 106-114
DOI: 10.1145/3209542.3209547

Interactions of Zynq-7000 devices with general purpose computers through PCI-express: A case study

Author(s): Artjom Rjabov, Alexander Sudnitson, Valery Sklyarov, Iouliia Skliarova
Published in: 2016 18th Mediterranean Electrotechnical Conference (MELECON), 2016, Page(s) 1-4
DOI: 10.1109/melcon.2016.7495400

Logic-based implementation of fault-tolerant routing in 3D network-on-chips

Author(s): Behrad Niazmand, Siavoosh Payandeh Azad, Jose Flich, Jaan Raik, Gert Jervan, Thomas Hollstein
Published in: 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2016, Page(s) 1-8
DOI: 10.1109/nocs.2016.7579317

Minimization of the High-Level Fault Model for Microprocessor Control Parts

Author(s): Raimund Ubar, Adeboye Stephen Oyeniran, Olusiji Medaiyese
Published in: 2018 16th Biennial Baltic Electronics Conference (BEC), 2018, Page(s) 1-4
DOI: 10.1109/bec.2018.8600980

Mining and modelling web user engagement: A survey on academic sites for framework establishment

Author(s): Tarmo Robal, Ahto Kalja
Published in: 2016 Portland International Conference on Management of Engineering and Technology (PICMET), 2016, Page(s) 1942-1952
DOI: 10.1109/picmet.2016.7806759

Multiple control fault testing in digital systems with high-level decision diagrams

Author(s): Raimund Ubar, Stephen Adeboye Oyeniran
Published in: 2016 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR), 2016, Page(s) 1-6
DOI: 10.1109/aqtr.2016.7501287

On automatic software-based self-test program generation based on high-level decision diagrams

Author(s): Artjom Jasnetski, Raimund Ubar, Anton Tsertov
Published in: 2016 17th Latin-American Test Symposium (LATS), 2016, Page(s) 177-177
DOI: 10.1109/latw.2016.7483357

On coverage of timing related faults at board level

Author(s): Artur Jutman, Igor Aleksejev, Sergei Devadze
Published in: 2016 21th IEEE European Test Symposium (ETS), 2016, Page(s) 1-2
DOI: 10.1109/ets.2016.7519295

On-line fault classification and handling in IEEE1687 based fault management system for complex SoCs

Author(s): Konstantin Shibin, Sergei Devadze, Artur Jutman
Published in: 2016 17th Latin-American Test Symposium (LATS), 2016, Page(s) 69-74
DOI: 10.1109/latw.2016.7483342

Ontology Design for Automatic Evaluation of Web User Interface Usability

Author(s): Tarmo Robal, Jevgeni Marenkov, Ahto Kalja
Published in: 2017 Portland International Conference on Management of Engineering and Technology (PICMET), 2017, Page(s) 1-8
DOI: 10.23919/picmet.2017.8125425

Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation

Author(s): Adeboye Stephen Oyeniran, Siavoosh Payandeh Azad, Raimund Ubar
Published in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-5
DOI: 10.1109/iscas.2018.8350936

Performance estimation of embedded applications on microcontrollers

Author(s): Priit Ruberg, Keijo Lass, Elvar Liiv, Peeter Ellervee
Published in: 2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2017, Page(s) 1-6
DOI: 10.1109/norchip.2017.8124964

Practicing start-up culture in teaching embedded systems

Author(s): Uljana Reinsalu, Siavoosh Payandeh Azad, Mairo Leier, Kalle Tammemae, Thomas Hollstein
Published in: 2016 11th European Workshop on Microelectronics Education (EWME), 2016, Page(s) 1-6
DOI: 10.1109/ewme.2016.7496463

RAM-based mergers for data sort and frequent item computation

Author(s): Artjom Rjabov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson
Published in: 2017 40th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO), 2017, Page(s) 176-181
DOI: 10.23919/mipro.2017.7973413

Reconfigurable systems in engineering education: Best practices and future trends

Author(s): Iouliia Skliarova, Valery Sklyarov, Alexander Sudnitson, Margus Kruus
Published in: 2017 IEEE Global Engineering Education Conference (EDUCON), 2017, Page(s) 1084-1088
DOI: 10.1109/educon.2017.7942983

Reliable health monitoring and fault management infrastructure based on embedded instrumentation and IEEE 1687

Author(s): Artur Jutman, Konstantin Shibin, Sergei Devadze
Published in: 2016 IEEE AUTOTESTCON, 2016, Page(s) 1-10
DOI: 10.1109/autest.2016.7589605

Scalable algorithm for structural fault collapsing in digital circuits

Author(s): Raimund Ubar, Lembit Jurimagi, Elmet Orasson, Jaan Raik
Published in: 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2015, Page(s) 171-176
DOI: 10.1109/vlsi-soc.2015.7314411

Self-driving car ISEAUTO for research and education

Author(s): Raivo Sell, Mairo Leier, Anton Rassolkin, Juhan-Peep Ernits
Published in: 2018 19th International Conference on Research and Education in Mechatronics (REM), 2018, Page(s) 111-116
DOI: 10.1109/rem.2018.8421793

SoCDep 2 : A framework for dependable task deployment on many-core systems under mixed-criticality constraints

Author(s): Siavoosh Payandeh Azad, Behrad Niazmand, Peeter Ellervee, Jaan Raik, Gert Jervan, Thomas Hollstein
Published in: 2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2016, Page(s) 1-6
DOI: 10.1109/recosoc.2016.7533903

Standards-based tools and services for building lifelong learning pathways

Author(s): C. Sgouropoulou, I. Voyiatzis, A. Koutoumanos, S. Hamdioui, P. Pouyan, M. Comte, P. Prinetto, G. Airo Farulla, P. Ellervee, C. Delgado Kloos, R. Crespo Garcia
Published in: 2017 IEEE Global Engineering Education Conference (EDUCON), 2017, Page(s) 1619-1621
DOI: 10.1109/educon.2017.7943065

Stationary vs. Non-stationary Mobile Learning in MOOCs

Author(s): Yue Zhao, Tarmo Robal, Christoph Lofi, Claudia Hauff
Published in: Adjunct Publication of the 26th Conference on User Modeling, Adaptation and Personalization - UMAP '18, 2018, Page(s) 299-303
DOI: 10.1145/3213586.3225241

Timing-critical path analysis with structurally synthesized BDDs

Author(s): Raimund Ubar, Lembit Jurimagi, Maksim Jenihhin, Jaan Raik, Niyi-Leigh Olugbenga, Vladimir Viies
Published in: 2018 7th Mediterranean Conference on Embedded Computing (MECO), 2018, Page(s) 1-6
DOI: 10.1109/meco.2018.8406051

TransMem: A memory architecture to support dynamic remapping and parallelism in low power high performance CGRAs

Author(s): Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Ahmed Hemani, Peter Ellervee
Published in: 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2016, Page(s) 92-99
DOI: 10.1109/patmos.2016.7833431

A framework for improving web application user interfaces through immediate evaluation

Author(s): Marenkov, Jevgeni; Robal, Tarmo; Kalja, Ahto
Published in: 2016
DOI: 10.3233/978-1-61499-714-6-283

Automated software-based self-test generation for microprocessors

Author(s): Artjom Jasnetski, Raimund Ubar, Anton Tsertov
Published in: "2017 MIXDES - 24th International Conference ""Mixed Design of Integrated Circuits and Systems", 2017, Page(s) 453-458
DOI: 10.23919/mixdes.2017.8005252

Comparison of Predictive Equations for Basal Metabolic Rate

Author(s): Allik, A.; Mägi, S.; Pilt, K.; Karai, D.; Fridolin I.; Leier, M.; Jervan, G.
Published in: 2017

Refactoring - key to success for constantly developed projects

Author(s): Põld, Janari; Kalja, Ahto; Robal, Tarmo
Published in: 2017
DOI: 10.3233/978-1-61499-720-7-13

Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs

Author(s): Francesco Pellerey, Maksim Jenihhin, Giovanni Squillero, Jaan Raik, Matteo Sonza Reorda, Valentin Tihhomirov, Raimund Ubar
Published in: 2016 IEEE 25th Asian Test Symposium (ATS), 2016, Page(s) 304-309
DOI: 10.1109/ATS.2016.57

Designing reliable cyber-physical systems overview associated to the special session at FDL'16

Author(s): Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon Ter Braak, Sergei Devadze, Goerschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Konighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Rock, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
Published in: 2016 Forum on Specification and Design Languages (FDL), 2016, Page(s) 1-8
DOI: 10.1109/FDL.2016.7880382

Automated minimization of concurrent online checkers for Network-on-Chips

Author(s): Pietro Saltarelli, Behrad Niazmand, Ranganathan Hariharan, Jaan Raik, Gert Jervan, Thomas Hollstein
Published in: 2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015, Page(s) 1-8
DOI: 10.1109/ReCoSoC.2015.7238079

A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers

Author(s): Pietro Saltarelli, Behrad Niazmand, Jaan Raik, Ranganathan Hariharan, Gert Jervan, Thomas Hollstein
Published in: 2015 Euromicro Conference on Digital System Design, 2015, Page(s) 288-292
DOI: 10.1109/DSD.2015.15

FSMD RTL Design Manipulation for Clock Interface Abstraction

Author(s): Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan.
Published in: International Conference on Advances in Computing, Communications and Informatics (ICACCI), Kochi, India, August 10-13, 2015, 2015, Page(s) 1-6

A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers

Author(s): Pietro Saltarelli, Behrad Niazmand, Jaan Raik, Vineeth Govind, Thomas Hollstein, Gert Jervan, Ranganathan Hariharan
Published in: Proceedings of the 9th International Symposium on Networks-on-Chip - NOCS '15, 2015, Page(s) 1-8
DOI: 10.1145/2786572.2788713

Rejuvenation of Nanoscale Logic at NBTI-Critical Paths Using Evolutionary TPG

Author(s): Palermo, N.; Tihhomirov, V.; Copetti, T.S.; Jenihhin, M.; Raik, J.; Kostin, S.; Gaudesi, M.; Squillero, G.; Sonza Reorda, M.; Vargas, F.; Bolzani Poehls, L.
Published in: 16th IEEE Latin-American Test Symposium March 25 - 27, 2015, Puerto Vallarta, Mexico, 2015, Page(s) 1-6

Scalable Algorithm for Structural Fault Collapsing in Digital Circuits

Author(s): Ubar, Raimund; Jürimägi, Lembit; Orasson, Elmet; Raik, Jaan
Published in: IFIP/IEEE International Conference on Very Large Scale Integration - VLSI-SoC'2015, 2015, Page(s) 1-6

New Fault Models and Self-Test Generation for Microprocessors using High-Level Decision Diagrams

Author(s): Jasnetski, Artjom; Raik, Jaan; Tsertov, Anton; Ubar, Raimund
Published in: IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems - DDECS, 2015, Page(s) 1-6

SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic

Author(s): Kostin, Sergei; Raik, Jaan; Ubar, Raimund; Jenihhin, Maksim; Copetti, Thiago; Vargas, Fabian; Bolzani Poehls, Leticia
Published in: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2015, Belgrade, Serbia, 2015, Page(s) 1-6

SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores

Author(s): Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan
Published in: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2015, Belgrade, Serbia, 2015, Page(s) 1-4

Advanced Technical Education in the Age of Cyber Physical Systems

Author(s): Vierhaus, Heinrich; Raik, Jaan; Ubar, Raimund
Published in: Proceedings of the 10th European Workshop on Microelectronics Education – EWME, 2014, Page(s) 1-4

Abstraction of clock interface for conversion of RTL VHDL to SystemC

Author(s): Syed Saif Abrar, Maksim Jenihhin, Jaan Raik
Published in: 2014 IEEE International Advance Computing Conference (IACC), 2014, Page(s) 50-55
DOI: 10.1109/IAdCC.2014.6779293

Critical Path Tracing based Simulation of Transition Delay Faults

Author(s): Kõusaar, J.; Ubar, R.; Devadze, S.; Raik, J.
Published in: 17th Euromicro Conference on Digital System Design, Verona, Italy, August 27-29, 2014, 2014

Diagnostic Test Generation for Statistical Bug Localization using Evolutionary Computation

Author(s): Gaudesi, Marco; Jenihhin, Maksim; Raik, Jaan; Sanchez, Ernesto; Squillero, Giovanni; Tihomirov, Valentin; Ubar, Raimund
Published in: Genetic and Evolutionary Computation Conference, Vancouver, BC, Canada, July 12-16, 2014, 2014, Page(s) 1-6

Assessment of diagnostic test for automated bug localization

Author(s): Valentin Tihhomirov, Anton Tsepurov, Maksim Jenihhin, Jaan Raik, Raimund Ubar
Published in: 2013 14th Latin American Test Workshop - LATW, 2013, Page(s) 1-6
DOI: 10.1109/LATW.2013.6562665

Extended Checkers for Logic-Based Distributed Routing in Network-on-Chips

Author(s): Niazmand, Behrad; Hariharan, Ranganathan; Govind, Vineeth; Jervan, Gert; Hollstein, Thomas; Raik, Jaan
Published in: Baltic Electronic Conference, Laulasmaa, Estonia, 2014, Page(s) 1-4

Extensible Open-Source Framework for Translating RTL VHDL IP Cores to SystemC

Author(s): Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan
Published in: 15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Karlovy Vary, Czech Republic, April 8-10, 2013, 2013, Page(s) 112-115

At-speed self-testing of high-performance pipe-lined processing architectures

Author(s): Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min
Published in: 2013 NORCHIP, 2013, Page(s) 1-6
DOI: 10.1109/NORCHIP.2013.6702000

Performance Analysis of Cosimulating Processor Core in VHDL and SystemC




Identifying NBTI-Critical Paths in Nanoscale Logic

Author(s): Ubar, Raimund; Vargas, Fabian; Jenihhin, Maksim; Raik, Jaan; Kostin, Serge; Bolzani Poehls, Letícia
Published in: Proceedings of the 16th Euromicro Conference on Digital System Design, 2013, Page(s) 136–141

Synthesis of Multiple Fault Oriented Test Groups from Single Fault Test Sets




Design-Time Web Usability Evaluation with Guideliner

Author(s): Jevgeni Marenkov, Tarmo Robal, Ahto Kalja
Published in: Complex Systems Informatics and Modeling Quarterly, Issue 15, 2018, Page(s) 90-109, ISSN 2255-9922
DOI: 10.7250/csimq.2018-15.05