Twinning to Strengthen Tallinn University of Technology’s Research and Innovation Capacity in Nanoelectronics Based Dependable Cyber-Physical Systems

CORDIS oferuje możliwość skorzystania z odnośników do publicznie dostępnych publikacji i rezultatów projektów realizowanych w ramach programów ramowych HORYZONT.

Odnośniki do rezultatów i publikacji związanych z poszczególnymi projektami 7PR, a także odnośniki do niektórych konkretnych kategorii wyników, takich jak zbiory danych i oprogramowanie, są dynamicznie pobierane z systemu OpenAIRE .

Rezultaty

Project newsletters

1-2 newsletters/year over the duration of the project.

Promotion guide about TUT

Promotion guide about TUT.

Project website
Project leaflet and poster

• Project leaflet (2 pages, A4 size) and Powerpoint presentation providing overview of the project • Project poster (A1 size)

Publikacje

Extended Checkers for Logic-Based Distributed Routing in Network-on-Chips

Autorzy: Niazmand, Behrad; Hariharan, Ranganathan; Govind, Vineeth; Jervan, Gert; Hollstein, Thomas; Raik, Jaan
Opublikowane w: Baltic Electronic Conference, Laulasmaa, Estonia, 2014, Strona(/y) 1-4
Wydawca: IEEE

A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers

Autorzy: Pietro Saltarelli, Behrad Niazmand, Jaan Raik, Vineeth Govind, Thomas Hollstein, Gert Jervan, Ranganathan Hariharan
Opublikowane w: Proceedings of the 9th International Symposium on Networks-on-Chip - NOCS '15, 2015, Strona(/y) 1-8, ISBN 9781450333962
Wydawca: ACM Press
DOI: 10.1145/2786572.2788713

FSMD RTL Design Manipulation for Clock Interface Abstraction

Autorzy: Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan.
Opublikowane w: International Conference on Advances in Computing, Communications and Informatics (ICACCI), Kochi, India, August 10-13, 2015, 2015, Strona(/y) 1-6
Wydawca: IEEE

Critical Path Tracing based Simulation of Transition Delay Faults

Autorzy: Kõusaar, J.; Ubar, R.; Devadze, S.; Raik, J.
Opublikowane w: 17th Euromicro Conference on Digital System Design, Verona, Italy, August 27-29, 2014, 2014
Wydawca: IEEE Computer Society

Identifying NBTI-Critical Paths in Nanoscale Logic

Autorzy: Ubar, Raimund; Vargas, Fabian; Jenihhin, Maksim; Raik, Jaan; Kostin, Serge; Bolzani Poehls, Letícia
Opublikowane w: Proceedings of the 16th Euromicro Conference on Digital System Design, 2013, Strona(/y) 136–141
Wydawca: IEEE Computer Society Press

Assessment of diagnostic test for automated bug localization

Autorzy: Valentin Tihhomirov, Anton Tsepurov, Maksim Jenihhin, Jaan Raik, Raimund Ubar
Opublikowane w: 2013 14th Latin American Test Workshop - LATW, 2013, Strona(/y) 1-6, ISBN 978-1-4799-0597-3
Wydawca: IEEE
DOI: 10.1109/LATW.2013.6562665

New Fault Models and Self-Test Generation for Microprocessors using High-Level Decision Diagrams

Autorzy: Jasnetski, Artjom; Raik, Jaan; Tsertov, Anton; Ubar, Raimund
Opublikowane w: IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems - DDECS, 2015, Strona(/y) 1-6
Wydawca: IEEE Computer Society Press

Abstraction of clock interface for conversion of RTL VHDL to SystemC

Autorzy: Syed Saif Abrar, Maksim Jenihhin, Jaan Raik
Opublikowane w: 2014 IEEE International Advance Computing Conference (IACC), 2014, Strona(/y) 50-55, ISBN 978-1-4799-2572-8
Wydawca: IEEE
DOI: 10.1109/IAdCC.2014.6779293

SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores

Autorzy: Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan
Opublikowane w: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2015, Belgrade, Serbia, 2015, Strona(/y) 1-4
Wydawca: IEEE Computer Society Press

Diagnostic Test Generation for Statistical Bug Localization using Evolutionary Computation

Autorzy: Gaudesi, Marco; Jenihhin, Maksim; Raik, Jaan; Sanchez, Ernesto; Squillero, Giovanni; Tihomirov, Valentin; Ubar, Raimund
Opublikowane w: Genetic and Evolutionary Computation Conference, Vancouver, BC, Canada, July 12-16, 2014, 2014, Strona(/y) 1-6
Wydawca: IEEE Computer Society Press

Comprehensive performance and robustness analysis of 2D turn models for network-on-chips

Autorzy: Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Thilo Kogge, Jaan Raik, Gert Jervan, Thomas Hollstein
Opublikowane w: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, Strona(/y) 1-4, ISBN 978-1-4673-6853-7
Wydawca: IEEE
DOI: 10.1109/ISCAS.2017.8050634

High-level test generation for processing elements in many-core systems

Autorzy: Adeboye Stephen Oyeniran, Raimund Ubar, Siavoosh Payandeh Azad, Jaan Raik
Opublikowane w: 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, Strona(/y) 1-8, ISBN 978-1-5386-3344-1
Wydawca: IEEE
DOI: 10.1109/ReCoSoC.2017.8016156

Fault-resilient NoC router with transparent resource allocation

Autorzy: Tsotne Putkaradze, Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik, Gert Jervan
Opublikowane w: 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, Strona(/y) 1-8, ISBN 978-1-5386-3344-1
Wydawca: IEEE
DOI: 10.1109/ReCoSoC.2017.8016161

Automated area and coverage optimization of minimal latency checkers

Autorzy: Siavoosh Payandeh Azad, Behrad Niazmand, Apneet Kaur Sandhu, Jaan Raik, Gert Jervan, Thomas Hollstein
Opublikowane w: 2017 22nd IEEE European Test Symposium (ETS), 2017, Strona(/y) 1-2, ISBN 978-1-5090-5457-2
Wydawca: IEEE
DOI: 10.1109/ETS.2017.7968211

From online fault detection to fault management in Network-on-Chips: A ground-up approach

Autorzy: Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Nevin George, Adeboye Stephen Oyeniran, Tsotne Putkaradze, Apneet Kaur, Jaan Raik, Gert Jervan, Raimund Ubar, Thomas Hollstein
Opublikowane w: 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2017, Strona(/y) 48-53, ISBN 978-1-5386-0472-4
Wydawca: IEEE
DOI: 10.1109/DDECS.2017.7934565

A scalable technique to identify true critical paths in sequential circuits

Autorzy: Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik
Opublikowane w: 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2017, Strona(/y) 152-157, ISBN 978-1-5386-0472-4
Wydawca: IEEE
DOI: 10.1109/DDECS.2017.7934568

Marginal PCB assembly defect detection on DDR3/4 memory bus

Autorzy: Sergei Odintsov, Artur Jutman, Sergei Devadze
Opublikowane w: 2017 IEEE International Test Conference (ITC), 2017, Strona(/y) 1-10, ISBN 978-1-5386-3413-4
Wydawca: IEEE
DOI: 10.1109/TEST.2017.8242070

Embedded instrumentation toolbox for screening marginal defects and outliers for production

Autorzy: Sergei Odintsov, Artur Jutman, Sergei Devadze, Igor Aleksejev
Opublikowane w: 2017 IEEE AUTOTESTCON, 2017, Strona(/y) 1-9, ISBN 978-1-5090-4922-6
Wydawca: IEEE
DOI: 10.1109/AUTEST.2017.8080516

Multi-view modeling for MPSoC design aspects

Autorzy: Juri Vain, Apneet Kaur, Leonidas Tsiopoulos, Jaan Raik, Maksim Jenihhin
Opublikowane w: 2018 16th Biennial Baltic Electronics Conference (BEC), 2018, Strona(/y) 1-6, ISBN 978-1-5386-7312-6
Wydawca: IEEE
DOI: 10.1109/bec.2018.8600986

A Hierarchical Approach for Devising Area Efficient Concurrent Online Checkers

Autorzy: Behrad Niazmand, Siavoosh Payandeh Azad, Tara Ghasempouri, Jaan Raik, Gert Jervan
Opublikowane w: 2018 IEEE International Test Conference in Asia (ITC-Asia), 2018, Strona(/y) 139-144, ISBN 978-1-5386-5180-3
Wydawca: IEEE
DOI: 10.1109/itc-asia.2018.00034

A novel random approach to diagnostic test generation

Autorzy: Emmanuel Ovie Osimiry, Raimund Ubar, Sergei Kostin, Jaan Raik
Opublikowane w: 2016 IEEE Nordic Circuits and Systems Conference (NORCAS), 2016, Strona(/y) 1-4, ISBN 978-1-5090-1095-0
Wydawca: IEEE
DOI: 10.1109/norchip.2016.7792915

A suite of IEEE 1687 benchmark networks

Autorzy: Anton Tsertov, Artur Jutman, Sergei Devadze, Matteo Sonza Reorda, Erik Larsson, Farrokh Ghani Zadegan, Riccardo Cantoro, Mehrdad Montazeri, Rene Krenz-Baath
Opublikowane w: 2016 IEEE International Test Conference (ITC), 2016, Strona(/y) 1-10, ISBN 978-1-4673-8773-6
Wydawca: IEEE
DOI: 10.1109/test.2016.7805840

A Synthesis-Agnostic Behavioral Fault Model for High Gate-Level Fault Coverage

Autorzy: Anton Karputkin, Jaan Raik
Opublikowane w: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, Strona(/y) 1124-1127, ISBN 978-3-9815370-7-9
Wydawca: Research Publishing Services
DOI: 10.3850/9783981537079_0260

A tool for random test generation targeting high diagnostic resolution

Autorzy: Emmanuel Ovie Osimiry, Sergei Kostin, Jaan Raik, Raimund Ubar
Opublikowane w: 2016 15th Biennial Baltic Electronics Conference (BEC), 2016, Strona(/y) 79-82, ISBN 978-1-5090-1393-7
Wydawca: IEEE
DOI: 10.1109/bec.2016.7743733

A tool set for teaching design-for-testability of digital circuits

Autorzy: S. Kostin, E. Orasson, R. Ubar
Opublikowane w: 2016 11th European Workshop on Microelectronics Education (EWME), 2016, Strona(/y) 1-6, ISBN 978-1-4673-8584-8
Wydawca: IEEE
DOI: 10.1109/ewme.2016.7496466

Activity classification for real-time wearable systems: Effect of window length, sampling frequency and number of features on classifier performance

Autorzy: Ardo Allik, Kristjan Pilt, Deniss Karai, Ivo Fridolin, Mairo Leier, Gert Jervan
Opublikowane w: 2016 IEEE EMBS Conference on Biomedical Engineering and Sciences (IECBES), 2016, Strona(/y) 460-464, ISBN 978-1-4673-7791-1
Wydawca: IEEE
DOI: 10.1109/iecbes.2016.7843493

Administration of the State Information System of the Estonian eGovernment

Autorzy: Ahto Kalja, Tarmo Robal, Triin Gailan
Opublikowane w: 2017 Portland International Conference on Management of Engineering and Technology (PICMET), 2017, Strona(/y) 1-7, ISBN 978-1-890843-36-6
Wydawca: IEEE
DOI: 10.23919/picmet.2017.8125312

An Automatic Approach to Evaluate Assertions' Quality Based on Data-Mining Metrics

Autorzy: Tara Ghasempouri, Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik
Opublikowane w: 2018 IEEE International Test Conference in Asia (ITC-Asia), 2018, Strona(/y) 61-66, ISBN 978-1-5386-5180-3
Wydawca: IEEE
DOI: 10.1109/itc-asia.2018.00021

AWAIT: An Ultra-Lightweight Soft-Error Mitigation Mechanism for Network-on-Chip Links

Autorzy: Karl Janson, Rene Pihlak, Siavoosh Payandeh Azad, Behrad Niazmand, Gert Jervan, Jaan Raik
Opublikowane w: 2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2018, Strona(/y) 1-6, ISBN 978-1-5386-7957-9
Wydawca: IEEE
DOI: 10.1109/recosoc.2018.8449374

Augmented Coaching Ecosystem for Non-obtrusive Adaptive Personalized Elderly Care on the basis of Cloud-Fog-Dew computing paradigm

Autorzy: Yu. Gordienko, S. Stirenko, O. Alienin, K. Skala, Z. Sojat, A. Rojbi, J.R. Lopez Benito, E. Artetxe Gonzalez, U. Lushchyk, L. Sajn, A. Llorente Coto, G. Jervan
Opublikowane w: 2017 40th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO), 2017, Strona(/y) 359-364, ISBN 978-953-233-090-8
Wydawca: IEEE
DOI: 10.23919/mipro.2017.7973449

Combined pseudo-exhaustive and deterministic testing of array multipliers

Autorzy: Adeboye Stephen Oyeniran, Siavoosh Payandeh Azad, Raimund Ubar
Opublikowane w: 2018 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR), 2018, Strona(/y) 1-6, ISBN 978-1-5386-2205-6
Wydawca: IEEE
DOI: 10.1109/aqtr.2018.8402708

Data type dependent energy consumption estimation

Autorzy: Priit Ruberg, Keijo Lass, Peeter Ellervee
Opublikowane w: 2016 IEEE Nordic Circuits and Systems Conference (NORCAS), 2016, Strona(/y) 1-5, ISBN 978-1-5090-1095-0
Wydawca: IEEE
DOI: 10.1109/norchip.2016.7792916

Developing a data acquisition system for measuring microcontroller energy consumption using LabVIEW

Autorzy: Priit Ruberg, Keijo Lass, Peeter Ellervee
Opublikowane w: 2016 15th Biennial Baltic Electronics Conference (BEC), 2016, Strona(/y) 123-126, ISBN 978-1-5090-1393-7
Wydawca: IEEE
DOI: 10.1109/bec.2016.7743744

Embedded software performance estimations at different compiler optimisation levels

Autorzy: Priit Ruberg, Keijo Lass, Elvar Liiv, Peeter Ellervee
Opublikowane w: 2017 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE), 2017, Strona(/y) 1-6, ISBN 978-1-5386-4137-8
Wydawca: IEEE
DOI: 10.1109/aieee.2017.8270530

Parallel Critical Path Tracing Fault Simulation in Sequential Circuits

Autorzy: Jaak Kousaar, Raimund Ubar, Sergei Kostin, Sergei Devadze, Jaan Raik
Opublikowane w: "2018 25th International Conference ""Mixed Design of Integrated Circuits and System"" (MIXDES)", 2018, Strona(/y) 305-310, ISBN 978-83-63578-14-5
Wydawca: IEEE
DOI: 10.23919/mixdes.2018.8436880

Fair and Individualized Project Teamwork Evaluation for an Engineering Course

Autorzy: Tarmo Robal
Opublikowane w: 2018 28th EAEEIE Annual Conference (EAEEIE), 2018, Strona(/y) 1-9, ISBN 978-1-5386-7711-7
Wydawca: IEEE
DOI: 10.1109/eaeeie.2018.8534256

Fall detection and activity recognition system for usage in smart work-wear

Autorzy: Mairo Leier, Gert Jervan, Ardo Allik, Kristjan Pilt, Deniss Karai, Ivo Fridolin
Opublikowane w: 2018 16th Biennial Baltic Electronics Conference (BEC), 2018, Strona(/y) 1-4, ISBN 978-1-5386-7312-6
Wydawca: IEEE
DOI: 10.1109/bec.2018.8600959

Conditional Fault Collapsing in Digital Circuits with Shared Structurally Synthesized BDDs

Autorzy: Lembit Jurimagi, Raimund Ubar
Opublikowane w: 2018 16th Biennial Baltic Electronics Conference (BEC), 2018, Strona(/y) 1-4, ISBN 978-1-5386-7312-6
Wydawca: IEEE
DOI: 10.1109/bec.2018.8600967

Gate-level modelling of NBTI-induced delays under process variations

Autorzy: Thiago Copetti, Guilherme Medeiros, Leticia Bolzani Poehls, Fabian Vargas, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Raimund Ubar
Opublikowane w: 2016 17th Latin-American Test Symposium (LATS), 2016, Strona(/y) 75-80, ISBN 978-1-5090-1331-9
Wydawca: IEEE
DOI: 10.1109/latw.2016.7483343

Guideliner - a Tool to Improve Web UI Development for Better Usability

Autorzy: Jevgeni Marenkov, Tarmo Robal, Ahto Kalja
Opublikowane w: Proceedings of the 8th International Conference on Web Intelligence, Mining and Semantics - WIMS '18, 2018, Strona(/y) 1-9, ISBN 9781-450354899
Wydawca: ACM Press
DOI: 10.1145/3227609.3227667

Handling of SETs on NoC Links by Exploitation of Inherent Redundancy in Circular Input Buffers

Autorzy: Karl Janson, Rene Pihlak, Siavoosh Payandeh Azad, Behrad Niazmand, Gert Jervan, Jaan Raik
Opublikowane w: 2018 16th Biennial Baltic Electronics Conference (BEC), 2018, Strona(/y) 1-4, ISBN 978-1-5386-7312-6
Wydawca: IEEE
DOI: 10.1109/bec.2018.8600989

Hardware implementation of face recognition using low precision representation

Autorzy: Sai Kumar Dwivedi, Siavoosh Payandeh Azad, Peeter Ellervee, Ratnakar Dash
Opublikowane w: 2016 15th Biennial Baltic Electronics Conference (BEC), 2016, Strona(/y) 63-66, ISBN 978-1-5090-1393-7
Wydawca: IEEE
DOI: 10.1109/bec.2016.7743729

Hardware-based systems for partial sorting of streaming data

Autorzy: Artjom Rjabov
Opublikowane w: 2016 15th Biennial Baltic Electronics Conference (BEC), 2016, Strona(/y) 59-62, ISBN 978-1-5090-1393-7
Wydawca: IEEE
DOI: 10.1109/bec.2016.7743728

Hierarchical temporal memory implementation on FPGA using LFSR based spatial pooler address space generator

Autorzy: Madis Kerner, Kalle Tammemae
Opublikowane w: 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2017, Strona(/y) 92-95, ISBN 978-1-5386-0472-4
Wydawca: IEEE
DOI: 10.1109/ddecs.2017.7934577

Hierarchical Timing-Critical Paths Analysis in Sequential Circuits

Autorzy: Lembit Jurimagi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Sergei Kostin
Opublikowane w: 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2018, Strona(/y) 1-6, ISBN 978-1-5386-6365-3
Wydawca: IEEE
DOI: 10.1109/patmos.2018.8464176

High-level modeling and testing of multiple control faults in digital systems

Autorzy: Artjom Jasnetski, Stephen Adeboye Oyeniran, Anton Tsertov, Mario Scholzel, Raimund Ubar
Opublikowane w: 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016, Strona(/y) 1-6, ISBN 978-1-5090-2467-4
Wydawca: IEEE
DOI: 10.1109/ddecs.2016.7482445

High-level test data generation for software-based self-test in microprocessors

Autorzy: Adeboye Stephen Oyeniran, Artjom Jasnetski, Anton Tsertov, Raimund Ubar
Opublikowane w: 2017 6th Mediterranean Conference on Embedded Computing (MECO), 2017, Strona(/y) 1-6, ISBN 978-1-5090-6742-8
Wydawca: IEEE
DOI: 10.1109/meco.2017.7977167

IEEE 1687 Compliant Ecosystem for Embedded Instrumentation Access and In-Field Health Monitoring

Autorzy: Anton Tsertov, Artur Jutman, Konstantin Shibin, Sergei Devadze
Opublikowane w: 2018 IEEE AUTOTESTCON, 2018, Strona(/y) 1-9, ISBN 978-1-5386-5223-7
Wydawca: IEEE
DOI: 10.1109/autest.2018.8532559

In-Field Detection of Degradation on PCB Assembly High-Speed Buses

Autorzy: Sergei Odintsov
Opublikowane w: 2018 IEEE AUTOTESTCON, 2018, Strona(/y) 1-6, ISBN 978-1-5386-5223-7
Wydawca: IEEE
DOI: 10.1109/autest.2018.8532547

Understanding MPSoCs - exploiting memory microarchitectural vulnerabilities of high performance NoC-based MPSoCs

Autorzy: Johanna Sepulveda, Cezar Reinbrecht, Siavoosh Payandeh Azad, Behrad Niazmand, Gert Jervan
Opublikowane w: Proceedings of the 18th International Conference on Embedded Computer Systems Architectures, Modeling, and Simulation - SAMOS '18, 2018, Strona(/y) 162-166, ISBN 9781-450364942
Wydawca: ACM Press
DOI: 10.1145/3229631.3239367

IntelliEye - Enhancing MOOC Learners' Video Watching Experience through Real-Time Attention Tracking

Autorzy: Tarmo Robal, Yue Zhao, Christoph Lofi, Claudia Hauff
Opublikowane w: Proceedings of the 29th on Hypertext and Social Media - HT '18, 2018, Strona(/y) 106-114, ISBN 9781-450354271
Wydawca: ACM Press
DOI: 10.1145/3209542.3209547

Interactions of Zynq-7000 devices with general purpose computers through PCI-express: A case study

Autorzy: Artjom Rjabov, Alexander Sudnitson, Valery Sklyarov, Iouliia Skliarova
Opublikowane w: 2016 18th Mediterranean Electrotechnical Conference (MELECON), 2016, Strona(/y) 1-4, ISBN 978-1-5090-0058-6
Wydawca: IEEE
DOI: 10.1109/melcon.2016.7495400

Logic-based implementation of fault-tolerant routing in 3D network-on-chips

Autorzy: Behrad Niazmand, Siavoosh Payandeh Azad, Jose Flich, Jaan Raik, Gert Jervan, Thomas Hollstein
Opublikowane w: 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2016, Strona(/y) 1-8, ISBN 978-1-4673-9030-9
Wydawca: IEEE
DOI: 10.1109/nocs.2016.7579317

Minimization of the High-Level Fault Model for Microprocessor Control Parts

Autorzy: Raimund Ubar, Adeboye Stephen Oyeniran, Olusiji Medaiyese
Opublikowane w: 2018 16th Biennial Baltic Electronics Conference (BEC), 2018, Strona(/y) 1-4, ISBN 978-1-5386-7312-6
Wydawca: IEEE
DOI: 10.1109/bec.2018.8600980

Mining and modelling web user engagement: A survey on academic sites for framework establishment

Autorzy: Tarmo Robal, Ahto Kalja
Opublikowane w: 2016 Portland International Conference on Management of Engineering and Technology (PICMET), 2016, Strona(/y) 1942-1952
Wydawca: IEEE
DOI: 10.1109/picmet.2016.7806759

Multiple control fault testing in digital systems with high-level decision diagrams

Autorzy: Raimund Ubar, Stephen Adeboye Oyeniran
Opublikowane w: 2016 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR), 2016, Strona(/y) 1-6, ISBN 978-1-4673-8692-0
Wydawca: IEEE
DOI: 10.1109/aqtr.2016.7501287

On automatic software-based self-test program generation based on high-level decision diagrams

Autorzy: Artjom Jasnetski, Raimund Ubar, Anton Tsertov
Opublikowane w: 2016 17th Latin-American Test Symposium (LATS), 2016, Strona(/y) 177-177, ISBN 978-1-5090-1331-9
Wydawca: IEEE
DOI: 10.1109/latw.2016.7483357

On coverage of timing related faults at board level

Autorzy: Artur Jutman, Igor Aleksejev, Sergei Devadze
Opublikowane w: 2016 21th IEEE European Test Symposium (ETS), 2016, Strona(/y) 1-2, ISBN 978-1-4673-9659-2
Wydawca: IEEE
DOI: 10.1109/ets.2016.7519295

On-line fault classification and handling in IEEE1687 based fault management system for complex SoCs

Autorzy: Konstantin Shibin, Sergei Devadze, Artur Jutman
Opublikowane w: 2016 17th Latin-American Test Symposium (LATS), 2016, Strona(/y) 69-74, ISBN 978-1-5090-1331-9
Wydawca: IEEE
DOI: 10.1109/latw.2016.7483342

Ontology Design for Automatic Evaluation of Web User Interface Usability

Autorzy: Tarmo Robal, Jevgeni Marenkov, Ahto Kalja
Opublikowane w: 2017 Portland International Conference on Management of Engineering and Technology (PICMET), 2017, Strona(/y) 1-8, ISBN 978-1-890843-36-6
Wydawca: IEEE
DOI: 10.23919/picmet.2017.8125425

Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation

Autorzy: Adeboye Stephen Oyeniran, Siavoosh Payandeh Azad, Raimund Ubar
Opublikowane w: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Strona(/y) 1-5, ISBN 978-1-5386-4881-0
Wydawca: IEEE
DOI: 10.1109/iscas.2018.8350936

Performance estimation of embedded applications on microcontrollers

Autorzy: Priit Ruberg, Keijo Lass, Elvar Liiv, Peeter Ellervee
Opublikowane w: 2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2017, Strona(/y) 1-6, ISBN 978-1-5386-2844-7
Wydawca: IEEE
DOI: 10.1109/norchip.2017.8124964

Practicing start-up culture in teaching embedded systems

Autorzy: Uljana Reinsalu, Siavoosh Payandeh Azad, Mairo Leier, Kalle Tammemae, Thomas Hollstein
Opublikowane w: 2016 11th European Workshop on Microelectronics Education (EWME), 2016, Strona(/y) 1-6, ISBN 978-1-4673-8584-8
Wydawca: IEEE
DOI: 10.1109/ewme.2016.7496463

QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications

Autorzy: Serhiy Avramenko, Siavoosh Payandeh Azad, Stefano Esposito, Behrad Niazmand, Massimo Violante, Jaan Raik, Maksim Jenihhin
Opublikowane w: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2018, Strona(/y) 67-72, ISBN 978-1-5386-5754-6
Wydawca: IEEE
DOI: 10.1109/ddecs.2018.00-10

RAM-based mergers for data sort and frequent item computation

Autorzy: Artjom Rjabov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson
Opublikowane w: 2017 40th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO), 2017, Strona(/y) 176-181, ISBN 978-953-233-090-8
Wydawca: IEEE
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Reconfigurable systems in engineering education: Best practices and future trends

Autorzy: Iouliia Skliarova, Valery Sklyarov, Alexander Sudnitson, Margus Kruus
Opublikowane w: 2017 IEEE Global Engineering Education Conference (EDUCON), 2017, Strona(/y) 1084-1088, ISBN 978-1-5090-5467-1
Wydawca: IEEE
DOI: 10.1109/educon.2017.7942983

Reliable health monitoring and fault management infrastructure based on embedded instrumentation and IEEE 1687

Autorzy: Artur Jutman, Konstantin Shibin, Sergei Devadze
Opublikowane w: 2016 IEEE AUTOTESTCON, 2016, Strona(/y) 1-10, ISBN 978-1-5090-0790-5
Wydawca: IEEE
DOI: 10.1109/autest.2016.7589605

Replication-Based Deterministic Testing of 2-Dimensional Arrays with Highly Interrelated Cells

Autorzy: Siavoosh Payandeh Azad, Adeboye Stephen Oyeniran, Raimund Ubar
Opublikowane w: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2018, Strona(/y) 21-26, ISBN 978-1-5386-5754-6
Wydawca: IEEE
DOI: 10.1109/ddecs.2018.00011

Scalable algorithm for structural fault collapsing in digital circuits

Autorzy: Raimund Ubar, Lembit Jurimagi, Elmet Orasson, Jaan Raik
Opublikowane w: 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2015, Strona(/y) 171-176, ISBN 978-1-4673-9140-5
Wydawca: IEEE
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Self-driving car ISEAUTO for research and education

Autorzy: Raivo Sell, Mairo Leier, Anton Rassolkin, Juhan-Peep Ernits
Opublikowane w: 2018 19th International Conference on Research and Education in Mechatronics (REM), 2018, Strona(/y) 111-116, ISBN 978-1-5386-5413-2
Wydawca: IEEE
DOI: 10.1109/rem.2018.8421793

SoCDep 2 : A framework for dependable task deployment on many-core systems under mixed-criticality constraints

Autorzy: Siavoosh Payandeh Azad, Behrad Niazmand, Peeter Ellervee, Jaan Raik, Gert Jervan, Thomas Hollstein
Opublikowane w: 2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2016, Strona(/y) 1-6, ISBN 978-1-5090-2520-6
Wydawca: IEEE
DOI: 10.1109/recosoc.2016.7533903

Software-Level TMR Approach for On-Board Data Processing in Space Applications

Autorzy: Karl Janson, Carl Johann Treudler, Thomas Hollstein, Jaan Raik, Maksim Jenihhin, Goerschwin Fey
Opublikowane w: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2018, Strona(/y) 147-152, ISBN 978-1-5386-5754-6
Wydawca: IEEE
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Standards-based tools and services for building lifelong learning pathways

Autorzy: C. Sgouropoulou, I. Voyiatzis, A. Koutoumanos, S. Hamdioui, P. Pouyan, M. Comte, P. Prinetto, G. Airo Farulla, P. Ellervee, C. Delgado Kloos, R. Crespo Garcia
Opublikowane w: 2017 IEEE Global Engineering Education Conference (EDUCON), 2017, Strona(/y) 1619-1621, ISBN 978-1-5090-5467-1
Wydawca: IEEE
DOI: 10.1109/educon.2017.7943065

Stationary vs. Non-stationary Mobile Learning in MOOCs

Autorzy: Yue Zhao, Tarmo Robal, Christoph Lofi, Claudia Hauff
Opublikowane w: Adjunct Publication of the 26th Conference on User Modeling, Adaptation and Personalization - UMAP '18, 2018, Strona(/y) 299-303, ISBN 9781-450357845
Wydawca: ACM Press
DOI: 10.1145/3213586.3225241

Timing-critical path analysis with structurally synthesized BDDs

Autorzy: Raimund Ubar, Lembit Jurimagi, Maksim Jenihhin, Jaan Raik, Niyi-Leigh Olugbenga, Vladimir Viies
Opublikowane w: 2018 7th Mediterranean Conference on Embedded Computing (MECO), 2018, Strona(/y) 1-6, ISBN 978-1-5386-5683-9
Wydawca: IEEE
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TransMem: A memory architecture to support dynamic remapping and parallelism in low power high performance CGRAs

Autorzy: Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Ahmed Hemani, Peter Ellervee
Opublikowane w: 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2016, Strona(/y) 92-99, ISBN 978-1-5090-0733-2
Wydawca: IEEE
DOI: 10.1109/patmos.2016.7833431

Webcam-based Attention Tracking in Online Learning - A Feasibility Study

Autorzy: Tarmo Robal, Yue Zhao, Christoph Lofi, Claudia Hauff
Opublikowane w: Proceedings of the 2018 Conference on Human Information Interaction&Retrieval - IUI '18, 2018, Strona(/y) 189-197, ISBN 9781-450349451
Wydawca: ACM Press
DOI: 10.1145/3172944.3172987

Universal mitigation of NBTI-induced aging by design randomization

Autorzy: Maksim Jenihhin, Alexander Kamkin, Zainalabedin Navabi, Somayeh Sadeghi-Kohan
Opublikowane w: 2016 IEEE East-West Design & Test Symposium (EWDTS), 2016, Strona(/y) 1-5, ISBN 978-1-5090-0693-9
Wydawca: IEEE
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A framework for improving web application user interfaces through immediate evaluation

Autorzy: Marenkov, Jevgeni; Robal, Tarmo; Kalja, Ahto
Opublikowane w: 2016
Wydawca: IOS Press
DOI: 10.3233/978-1-61499-714-6-283

Automated software-based self-test generation for microprocessors

Autorzy: Artjom Jasnetski, Raimund Ubar, Anton Tsertov
Opublikowane w: "2017 MIXDES - 24th International Conference ""Mixed Design of Integrated Circuits and Systems", 2017, Strona(/y) 453-458, ISBN 978-83-63578-12-1
Wydawca: IEEE
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Comparison of Predictive Equations for Basal Metabolic Rate

Autorzy: Allik, A.; Mägi, S.; Pilt, K.; Karai, D.; Fridolin I.; Leier, M.; Jervan, G.
Opublikowane w: 2017
Wydawca: Springer

Refactoring - key to success for constantly developed projects

Autorzy: Põld, Janari; Kalja, Ahto; Robal, Tarmo
Opublikowane w: 2017
Wydawca: IOS Press
DOI: 10.3233/978-1-61499-720-7-13

BASTION: Board and SoC test instrumentation for ageing and no failure found

Autorzy: Artur Jutman, Christophe Lotz, Erik Larsson, Matteo Sonza Reorda, Maksim Jenihhin, Jaan Raik, Hans Kerkhoff, Rene Krenz-Baath, Piet Engelke
Opublikowane w: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, Strona(/y) 115-120, ISBN 978-3-9815370-8-6
Wydawca: IEEE
DOI: 10.23919/DATE.2017.7926968

Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs

Autorzy: Francesco Pellerey, Maksim Jenihhin, Giovanni Squillero, Jaan Raik, Matteo Sonza Reorda, Valentin Tihhomirov, Raimund Ubar
Opublikowane w: 2016 IEEE 25th Asian Test Symposium (ATS), 2016, Strona(/y) 304-309, ISBN 978-1-5090-3809-1
Wydawca: IEEE
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Designing reliable cyber-physical systems overview associated to the special session at FDL'16

Autorzy: Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon Ter Braak, Sergei Devadze, Goerschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Konighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Rock, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
Opublikowane w: 2016 Forum on Specification and Design Languages (FDL), 2016, Strona(/y) 1-8, ISBN 979-10-92279-17-7
Wydawca: IEEE
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A comprehensive methodology for stress procedures evaluation and comparison for Burn-In of automotive SoC

Autorzy: D. Appello, P. Bernardi, G. Giacopelli, A. Motta, A. Pagani, G. Pollaccia, C. Rabbi, M. Restifo, P. Ruberg, E. Sanchez, C.M. Villa, F. Venini
Opublikowane w: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, Strona(/y) 646-649, ISBN 978-3-9815370-8-6
Wydawca: IEEE
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Automated minimization of concurrent online checkers for Network-on-Chips

Autorzy: Pietro Saltarelli, Behrad Niazmand, Ranganathan Hariharan, Jaan Raik, Gert Jervan, Thomas Hollstein
Opublikowane w: 2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015, Strona(/y) 1-8, ISBN 978-1-4673-7942-7
Wydawca: IEEE
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A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers

Autorzy: Pietro Saltarelli, Behrad Niazmand, Jaan Raik, Ranganathan Hariharan, Gert Jervan, Thomas Hollstein
Opublikowane w: 2015 Euromicro Conference on Digital System Design, 2015, Strona(/y) 288-292, ISBN 978-1-4673-8035-5
Wydawca: IEEE
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FSMD RTL Design Manipulation for Clock Interface Abstraction

A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers

Rejuvenation of Nanoscale Logic at NBTI-Critical Paths Using Evolutionary TPG

Autorzy: Palermo, N.; Tihhomirov, V.; Copetti, T.S.; Jenihhin, M.; Raik, J.; Kostin, S.; Gaudesi, M.; Squillero, G.; Sonza Reorda, M.; Vargas, F.; Bolzani Poehls, L.
Opublikowane w: 16th IEEE Latin-American Test Symposium March 25 - 27, 2015, Puerto Vallarta, Mexico, 2015, Strona(/y) 1-6
Wydawca: IEEE Computer Society Press

Scalable Algorithm for Structural Fault Collapsing in Digital Circuits

Autorzy: Ubar, Raimund; Jürimägi, Lembit; Orasson, Elmet; Raik, Jaan
Opublikowane w: IFIP/IEEE International Conference on Very Large Scale Integration - VLSI-SoC'2015, 2015, Strona(/y) 1-6
Wydawca: IEEE Computer Society Press

New Fault Models and Self-Test Generation for Microprocessors using High-Level Decision Diagrams

SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic

Autorzy: Kostin, Sergei; Raik, Jaan; Ubar, Raimund; Jenihhin, Maksim; Copetti, Thiago; Vargas, Fabian; Bolzani Poehls, Leticia
Opublikowane w: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2015, Belgrade, Serbia, 2015, Strona(/y) 1-6
Wydawca: IEEE Computer Society Press

SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores

Advanced Technical Education in the Age of Cyber Physical Systems

Autorzy: Vierhaus, Heinrich; Raik, Jaan; Ubar, Raimund
Opublikowane w: Proceedings of the 10th European Workshop on Microelectronics Education – EWME, 2014, Strona(/y) 1-4
Wydawca: IEEE Computer Society

Abstraction of clock interface for conversion of RTL VHDL to SystemC

Critical Path Tracing based Simulation of Transition Delay Faults

Autorzy: Kõusaar, J.; Ubar, R.; Devadze, S.; Raik, J.
Opublikowane w: 17th Euromicro Conference on Digital System Design, Verona, Italy, August 27-29, 2014, 2014
Wydawca: IEEE Computer Society

Diagnostic Test Generation for Statistical Bug Localization using Evolutionary Computation

Assessment of diagnostic test for automated bug localization

Extended Checkers for Logic-Based Distributed Routing in Network-on-Chips

Extensible Open-Source Framework for Translating RTL VHDL IP Cores to SystemC

Autorzy: Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan
Opublikowane w: 15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Karlovy Vary, Czech Republic, April 8-10, 2013, 2013, Strona(/y) 112-115
Wydawca: IEEE

At-speed self-testing of high-performance pipe-lined processing architectures

Autorzy: Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min
Opublikowane w: 2013 NORCHIP, 2013, Strona(/y) 1-6, ISBN 978-1-4799-1647-4
Wydawca: IEEE
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Performance Analysis of Cosimulating Processor Core in VHDL and SystemC

Autorzy: Syed, Saif Abrar; Shyam, Kiran A.; Jenihhin, Maksim; Raik, Jaan; Babu, C.
Opublikowane w: Proc. of 2nd IEEE International Conference on Advances in Computing, Communications & Informatics, 2013, Strona(/y) 1-6
Wydawca: IEEE

Identifying NBTI-Critical Paths in Nanoscale Logic

Synthesis of Multiple Fault Oriented Test Groups from Single Fault Test Sets

Autorzy: Ubar, Raimund; Kostin, Sergei; Raik, Jaan
Opublikowane w: 8th Int. Conference on Design & Technology of Integrated Systems in Nanoscale Era - DTIS’13, 2013, Strona(/y) 1-6
Wydawca: IEEE Computer Society

Extensible Open-Source Framework for Translating RTL VHDL IP Cores to SystemC

At-speed self-testing of high-performance pipe-lined processing architectures

Advanced Technical Education in the Age of Cyber Physical Systems

Rejuvenation of Nanoscale Logic at NBTI-Critical Paths Using Evolutionary TPG

A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers

Automated minimization of concurrent online checkers for Network-on-Chips

Performance Analysis of Cosimulating Processor Core in VHDL and SystemC

SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic

Scalable Algorithm for Structural Fault Collapsing in Digital Circuits

Synthesis of Multiple Fault Oriented Test Groups from Single Fault Test Sets

Functional self-test of high-performance pipe-lined signal processing architectures

Autorzy: Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min
Opublikowane w: Microprocessors and Microsystems, Numer 39/8, 2015, Strona(/y) 909-918, ISSN 0141-9331
Wydawca: Elsevier BV
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Automated Design Error Localization in RTL Designs

Autorzy: Maksim Jenihhin, Anton Tsepurov, Valentin Tihhomirov, Jaan Raik, Hanno Hantson, Raimund Ubar, Gunter Bartsch, JorgeHernan Meza Escobar, Heinz-Dietrich Wuttke
Opublikowane w: IEEE Design & Test, Numer 31/1, 2014, Strona(/y) 83-92, ISSN 2168-2356
Wydawca: IEEE Computer Society
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Automated design error debug using high-level decision diagrams and mutation operators

Autorzy: Jaan Raik, Urmas Repinski, Anton Chepurov, Hanno Hantson, Raimund Ubar, Maksim Jenihhin
Opublikowane w: Microprocessors and Microsystems, Numer 37/4-5, 2013, Strona(/y) 505-513, ISSN 0141-9331
Wydawca: Elsevier BV
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Fast identification of true critical paths in sequential circuits

Autorzy: Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Lembit Jürimägi
Opublikowane w: Microelectronics Reliability, Numer 81, 2018, Strona(/y) 252-261, ISSN 0026-2714
Wydawca: Elsevier BV
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Modeling and simulation of circuits with shared structurally synthesized BDDs

Autorzy: Raimund Ubar, Lembit Jürimägi, Jaan Raik, Vladimir Viies
Opublikowane w: Microprocessors and Microsystems, Numer 48, 2017, Strona(/y) 56-61, ISSN 0141-9331
Wydawca: Elsevier BV
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Health Management for Self-Aware SoCs Based on IEEE 1687 Infrastructure

Autorzy: Konstantin Shibin, Sergei Devadze, Artur Jutman, Martin Grabmann, Robin Pricken
Opublikowane w: IEEE Design & Test, Numer 34/6, 2017, Strona(/y) 27-35, ISSN 2168-2356
Wydawca: IEEE Computer Society
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Run-time reconfigurable instruments for advanced board-level testing

Autorzy: Igor Aleksejev, Artur Jutman, Sergei Devadze
Opublikowane w: IEEE Instrumentation & Measurement Magazine, Numer 20/4, 2017, Strona(/y) 23-30, ISSN 1094-6969
Wydawca: Institute of Electrical and Electronics Engineers
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Computing Sorted Subsets for Data Processing in Communicating Software/Hardware Control Systems

Autorzy: Valery Sklyarov, Iouliia Skliarova, Artjom Rjabov, Alexander Sudnitson
Opublikowane w: International Journal of Computers Communications & Control, Numer 11/1, 2015, Strona(/y) 126, ISSN 1841-9836
Wydawca: Agora University
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Fast Data Sort based on Searching Networks with Ring Pipeline

Autorzy: Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson
Opublikowane w: Elektronika ir Elektrotechnika, Numer 22/4, 2016, ISSN 1392-1215
Wydawca: Kauno Technologijos Universitetas
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Fast iterative circuits and RAM-based mergers to accelerate data sort in software/hardware systems

Autorzy: V Sklyarov, I Skliarova, A Rjabov, A Sudnitson
Opublikowane w: Proceedings of the Estonian Academy of Sciences, Numer 66/3, 2017, Strona(/y) 323, ISSN 1736-6046
Wydawca: Estonian Academy Publishers
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Guest Editorial: Implementation Issues in System-on-Chip

Autorzy: Peeter Ellervee, Jari Nurmi
Opublikowane w: Journal of Signal Processing Systems, Numer 87/3, 2017, Strona(/y) 269-270, ISSN 1939-8018
Wydawca: Springer Verlag
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Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures

Autorzy: Igor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin
Opublikowane w: Journal of Electronic Testing, Numer 32/3, 2016, Strona(/y) 245-255, ISSN 0923-8174
Wydawca: Kluwer Academic Publishers
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Polymorphic Configuration Architecture for CGRAs

Autorzy: Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Ahmed Hemani, Kolin Paul, Juha Plosila, Peeter Ellervee, Hannu Tenuhnen
Opublikowane w: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Numer 24/1, 2016, Strona(/y) 403-407, ISSN 1063-8210
Wydawca: Institute of Electrical and Electronics Engineers
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Surrogate Data Method Requires End-Matched Segmentation of Electroencephalographic Signals to Estimate Non-linearity

Autorzy: Laura Päeske, Maie Bachmann, Toomas Põld, Sara Pereira Mendes de Oliveira, Jaanus Lass, Jaan Raik, Hiie Hinrikus
Opublikowane w: Frontiers in Physiology, Numer 9, 2018, ISSN 1664-042X
Wydawca: Frontiers Research Foundation
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Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

Autorzy: Maksim Jenihhin, Giovanni Squillero, Thiago Santos Copetti, Valentin Tihhomirov, Sergei Kostin, Marco Gaudesi, Fabian Vargas, Jaan Raik, Matteo Sonza Reorda, Leticia Bolzani Poehls, Raimund Ubar, Guilherme Cardoso Medeiros
Opublikowane w: Journal of Electronic Testing, Numer 32/3, 2016, Strona(/y) 273-289, ISSN 0923-8174
Wydawca: Kluwer Academic Publishers
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Functional self-test of high-performance pipe-lined signal processing architectures

Autorzy: Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min
Opublikowane w: Microprocessors and Microsystems, Numer 01419331, 2015, Strona(/y) 909-918, ISSN 0141-9331
Wydawca: Elsevier BV
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Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra

Autorzy: Jaak Kõusaar, Raimund Ubar, Sergei Devadze, Jaan Raik
Opublikowane w: Microprocessors and Microsystems, Numer 01419331, 2015, Strona(/y) 1130-1138, ISSN 0141-9331
Wydawca: Elsevier BV
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Automated Design Error Localization in RTL Designs

Autorzy: Maksim Jenihhin, Anton Tsepurov, Valentin Tihhomirov, Jaan Raik, Hanno Hantson, Raimund Ubar, Gunter Bartsch, JorgeHernan Meza Escobar, Heinz-Dietrich Wuttke
Opublikowane w: IEEE Design & Test, Numer 21682356, 2014, Strona(/y) 83-92, ISSN 2168-2356
Wydawca: IEEE Computer Society
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Automated design error debug using high-level decision diagrams and mutation operators

Autorzy: Jaan Raik, Urmas Repinski, Anton Chepurov, Hanno Hantson, Raimund Ubar, Maksim Jenihhin
Opublikowane w: Microprocessors and Microsystems, Numer 01419331, 2013, Strona(/y) 505-513, ISSN 0141-9331
Wydawca: Elsevier BV
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Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra

Autorzy: Jaak Kõusaar, Raimund Ubar, Sergei Devadze, Jaan Raik
Opublikowane w: Microprocessors and Microsystems, Numer 39/8, 2015, Strona(/y) 1130-1138, ISSN 0141-9331
Wydawca: Elsevier BV
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Designing Reliable Cyber-Physical Systems

Autorzy: Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Goerschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Shlomit Koyfman, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
Opublikowane w: Lecture Notes in Electrical Engineering, 2018, Strona(/y) 15-38
Wydawca: Springer International Publishing
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A Study on Immediate Automatic Usability Evaluation of Web Application User Interfaces

Autorzy: Jevgeni Marenkov, Tarmo Robal, Ahto Kalja
Opublikowane w: Databases and Information Systems, Numer 615, 2016, Strona(/y) 257-271, ISBN 978-3-319-40179-9
Wydawca: Springer International Publishing
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A Tool for Design-Time Usability Evaluation of Web User Interfaces

Autorzy: Jevgeni Marenkov, Tarmo Robal, Ahto Kalja
Opublikowane w: Advances in Databases and Information Systems, Numer 10509, 2017, Strona(/y) 394-407, ISBN 978-3-319-66916-8
Wydawca: Springer International Publishing
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Can I Have a Mooc2Go, Please? On the Viability of Mobile vs. Stationary Learning

Autorzy: Yue Zhao, Tarmo Robal, Christoph Lofi, Claudia Hauff
Opublikowane w: Lifelong Technology-Enhanced Learning - 13th European Conference on Technology Enhanced Learning, EC-TEL 2018, Leeds, UK, September 3-5, 2018, Proceedings, Numer 11082, 2018, Strona(/y) 101-115, ISBN 978-3-319-98571-8
Wydawca: Springer International Publishing
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Classification Algorithm Improvement for Physical Activity Recognition in Maritime Environments

Autorzy: Ardo Allik, Kristjan Pilt, Deniss Karai, Ivo Fridolin, Mairo Leier, Gert Jervan
Opublikowane w: World Congress on Medical Physics and Biomedical Engineering 2018, Numer 68/3, 2019, Strona(/y) 13-17, ISBN 978-981-10-9022-6
Wydawca: Springer Singapore
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EEG Functional Connectivity Detects Seasonal Changes

Autorzy: Laura Päeske, Maie Bachmann, Jaan Raik, Hiie Hinrikus
Opublikowane w: World Congress on Medical Physics and Biomedical Engineering 2018 - June 3-8, 2018, Prague, Czech Republic (Vol.2), Numer 68/2, 2019, Strona(/y) 237-240, ISBN 978-981-10-9037-0
Wydawca: Springer Singapore
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Energy-Efficient Multi-fragment Markov Model Guided Online Model-Based Testing for MPSoC

Autorzy: Jüri Vain, Leonidas Tsiopoulos, Vyacheslav Kharchenko, Apneet Kaur, Maksim Jenihhin, Jaan Raik, Sven Nõmm
Opublikowane w: Green IT Engineering: Social, Business and Industrial Applications, Numer 171, 2019, Strona(/y) 273-297, ISBN 978-3-030-00252-7
Wydawca: Springer International Publishing
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Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs

Autorzy: Raimund Ubar, Lembit Jürimägi, Elmet Orasson, Jaan Raik
Opublikowane w: VLSI-SoC: Design for Reliability, Security, and Low Power, Numer 483, 2016, Strona(/y) 23-45, ISBN 978-3-319-46096-3
Wydawca: Springer International Publishing
DOI: 10.1007/978-3-319-46097-0_2

Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation

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Wydawca: Springer Berlin Heidelberg
DOI: 10.1007/978-3-662-45523-4_35

Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation

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Opublikowane w: Complex Systems Informatics and Modeling Quarterly, Numer 15, 2018, Strona(/y) 90-109, ISSN 2255-9922
Wydawca: 0302-9743
DOI: 10.7250/csimq.2018-15.05

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