Twinning to Strengthen Tallinn University of Technology’s Research and Innovation Capacity in Nanoelectronics Based Dependable Cyber-Physical Systems

CORDIS fornisce collegamenti ai risultati finali pubblici e alle pubblicazioni dei progetti ORIZZONTE.

I link ai risultati e alle pubblicazioni dei progetti del 7° PQ, così come i link ad alcuni tipi di risultati specifici come dataset e software, sono recuperati dinamicamente da .OpenAIRE .

Risultati finali

Project newsletters

1-2 newsletters/year over the duration of the project.

Promotion guide about TUT

Promotion guide about TUT.

Project website
Project leaflet and poster

• Project leaflet (2 pages, A4 size) and Powerpoint presentation providing overview of the project • Project poster (A1 size)

Pubblicazioni

Extended Checkers for Logic-Based Distributed Routing in Network-on-Chips

Autori: Niazmand, Behrad; Hariharan, Ranganathan; Govind, Vineeth; Jervan, Gert; Hollstein, Thomas; Raik, Jaan
Pubblicato in: Baltic Electronic Conference, Laulasmaa, Estonia, 2014, Pagina/e 1-4
Editore: IEEE

A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers

Autori: Pietro Saltarelli, Behrad Niazmand, Jaan Raik, Vineeth Govind, Thomas Hollstein, Gert Jervan, Ranganathan Hariharan
Pubblicato in: Proceedings of the 9th International Symposium on Networks-on-Chip - NOCS '15, 2015, Pagina/e 1-8, ISBN 9781450333962
Editore: ACM Press
DOI: 10.1145/2786572.2788713

FSMD RTL Design Manipulation for Clock Interface Abstraction

Autori: Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan.
Pubblicato in: International Conference on Advances in Computing, Communications and Informatics (ICACCI), Kochi, India, August 10-13, 2015, 2015, Pagina/e 1-6
Editore: IEEE

Critical Path Tracing based Simulation of Transition Delay Faults

Autori: Kõusaar, J.; Ubar, R.; Devadze, S.; Raik, J.
Pubblicato in: 17th Euromicro Conference on Digital System Design, Verona, Italy, August 27-29, 2014, 2014
Editore: IEEE Computer Society

Identifying NBTI-Critical Paths in Nanoscale Logic

Autori: Ubar, Raimund; Vargas, Fabian; Jenihhin, Maksim; Raik, Jaan; Kostin, Serge; Bolzani Poehls, Letícia
Pubblicato in: Proceedings of the 16th Euromicro Conference on Digital System Design, 2013, Pagina/e 136–141
Editore: IEEE Computer Society Press

Assessment of diagnostic test for automated bug localization

Autori: Valentin Tihhomirov, Anton Tsepurov, Maksim Jenihhin, Jaan Raik, Raimund Ubar
Pubblicato in: 2013 14th Latin American Test Workshop - LATW, 2013, Pagina/e 1-6, ISBN 978-1-4799-0597-3
Editore: IEEE
DOI: 10.1109/LATW.2013.6562665

New Fault Models and Self-Test Generation for Microprocessors using High-Level Decision Diagrams

Autori: Jasnetski, Artjom; Raik, Jaan; Tsertov, Anton; Ubar, Raimund
Pubblicato in: IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems - DDECS, 2015, Pagina/e 1-6
Editore: IEEE Computer Society Press

Abstraction of clock interface for conversion of RTL VHDL to SystemC

Autori: Syed Saif Abrar, Maksim Jenihhin, Jaan Raik
Pubblicato in: 2014 IEEE International Advance Computing Conference (IACC), 2014, Pagina/e 50-55, ISBN 978-1-4799-2572-8
Editore: IEEE
DOI: 10.1109/IAdCC.2014.6779293

SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores

Autori: Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan
Pubblicato in: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2015, Belgrade, Serbia, 2015, Pagina/e 1-4
Editore: IEEE Computer Society Press

Diagnostic Test Generation for Statistical Bug Localization using Evolutionary Computation

Autori: Gaudesi, Marco; Jenihhin, Maksim; Raik, Jaan; Sanchez, Ernesto; Squillero, Giovanni; Tihomirov, Valentin; Ubar, Raimund
Pubblicato in: Genetic and Evolutionary Computation Conference, Vancouver, BC, Canada, July 12-16, 2014, 2014, Pagina/e 1-6
Editore: IEEE Computer Society Press

Comprehensive performance and robustness analysis of 2D turn models for network-on-chips

Autori: Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Thilo Kogge, Jaan Raik, Gert Jervan, Thomas Hollstein
Pubblicato in: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, Pagina/e 1-4, ISBN 978-1-4673-6853-7
Editore: IEEE
DOI: 10.1109/ISCAS.2017.8050634

High-level test generation for processing elements in many-core systems

Autori: Adeboye Stephen Oyeniran, Raimund Ubar, Siavoosh Payandeh Azad, Jaan Raik
Pubblicato in: 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, Pagina/e 1-8, ISBN 978-1-5386-3344-1
Editore: IEEE
DOI: 10.1109/ReCoSoC.2017.8016156

Fault-resilient NoC router with transparent resource allocation

Autori: Tsotne Putkaradze, Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik, Gert Jervan
Pubblicato in: 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, Pagina/e 1-8, ISBN 978-1-5386-3344-1
Editore: IEEE
DOI: 10.1109/ReCoSoC.2017.8016161

Automated area and coverage optimization of minimal latency checkers

Autori: Siavoosh Payandeh Azad, Behrad Niazmand, Apneet Kaur Sandhu, Jaan Raik, Gert Jervan, Thomas Hollstein
Pubblicato in: 2017 22nd IEEE European Test Symposium (ETS), 2017, Pagina/e 1-2, ISBN 978-1-5090-5457-2
Editore: IEEE
DOI: 10.1109/ETS.2017.7968211

From online fault detection to fault management in Network-on-Chips: A ground-up approach

Autori: Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Nevin George, Adeboye Stephen Oyeniran, Tsotne Putkaradze, Apneet Kaur, Jaan Raik, Gert Jervan, Raimund Ubar, Thomas Hollstein
Pubblicato in: 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2017, Pagina/e 48-53, ISBN 978-1-5386-0472-4
Editore: IEEE
DOI: 10.1109/DDECS.2017.7934565

A scalable technique to identify true critical paths in sequential circuits

Autori: Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik
Pubblicato in: 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2017, Pagina/e 152-157, ISBN 978-1-5386-0472-4
Editore: IEEE
DOI: 10.1109/DDECS.2017.7934568

Marginal PCB assembly defect detection on DDR3/4 memory bus

Autori: Sergei Odintsov, Artur Jutman, Sergei Devadze
Pubblicato in: 2017 IEEE International Test Conference (ITC), 2017, Pagina/e 1-10, ISBN 978-1-5386-3413-4
Editore: IEEE
DOI: 10.1109/TEST.2017.8242070

Embedded instrumentation toolbox for screening marginal defects and outliers for production

Autori: Sergei Odintsov, Artur Jutman, Sergei Devadze, Igor Aleksejev
Pubblicato in: 2017 IEEE AUTOTESTCON, 2017, Pagina/e 1-9, ISBN 978-1-5090-4922-6
Editore: IEEE
DOI: 10.1109/AUTEST.2017.8080516

Multi-view modeling for MPSoC design aspects

Autori: Juri Vain, Apneet Kaur, Leonidas Tsiopoulos, Jaan Raik, Maksim Jenihhin
Pubblicato in: 2018 16th Biennial Baltic Electronics Conference (BEC), 2018, Pagina/e 1-6, ISBN 978-1-5386-7312-6
Editore: IEEE
DOI: 10.1109/bec.2018.8600986

A Hierarchical Approach for Devising Area Efficient Concurrent Online Checkers

Autori: Behrad Niazmand, Siavoosh Payandeh Azad, Tara Ghasempouri, Jaan Raik, Gert Jervan
Pubblicato in: 2018 IEEE International Test Conference in Asia (ITC-Asia), 2018, Pagina/e 139-144, ISBN 978-1-5386-5180-3
Editore: IEEE
DOI: 10.1109/itc-asia.2018.00034

A novel random approach to diagnostic test generation

Autori: Emmanuel Ovie Osimiry, Raimund Ubar, Sergei Kostin, Jaan Raik
Pubblicato in: 2016 IEEE Nordic Circuits and Systems Conference (NORCAS), 2016, Pagina/e 1-4, ISBN 978-1-5090-1095-0
Editore: IEEE
DOI: 10.1109/norchip.2016.7792915

A suite of IEEE 1687 benchmark networks

Autori: Anton Tsertov, Artur Jutman, Sergei Devadze, Matteo Sonza Reorda, Erik Larsson, Farrokh Ghani Zadegan, Riccardo Cantoro, Mehrdad Montazeri, Rene Krenz-Baath
Pubblicato in: 2016 IEEE International Test Conference (ITC), 2016, Pagina/e 1-10, ISBN 978-1-4673-8773-6
Editore: IEEE
DOI: 10.1109/test.2016.7805840

A Synthesis-Agnostic Behavioral Fault Model for High Gate-Level Fault Coverage

Autori: Anton Karputkin, Jaan Raik
Pubblicato in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, Pagina/e 1124-1127, ISBN 978-3-9815370-7-9
Editore: Research Publishing Services
DOI: 10.3850/9783981537079_0260

A tool for random test generation targeting high diagnostic resolution

Autori: Emmanuel Ovie Osimiry, Sergei Kostin, Jaan Raik, Raimund Ubar
Pubblicato in: 2016 15th Biennial Baltic Electronics Conference (BEC), 2016, Pagina/e 79-82, ISBN 978-1-5090-1393-7
Editore: IEEE
DOI: 10.1109/bec.2016.7743733

A tool set for teaching design-for-testability of digital circuits

Autori: S. Kostin, E. Orasson, R. Ubar
Pubblicato in: 2016 11th European Workshop on Microelectronics Education (EWME), 2016, Pagina/e 1-6, ISBN 978-1-4673-8584-8
Editore: IEEE
DOI: 10.1109/ewme.2016.7496466

Activity classification for real-time wearable systems: Effect of window length, sampling frequency and number of features on classifier performance

Autori: Ardo Allik, Kristjan Pilt, Deniss Karai, Ivo Fridolin, Mairo Leier, Gert Jervan
Pubblicato in: 2016 IEEE EMBS Conference on Biomedical Engineering and Sciences (IECBES), 2016, Pagina/e 460-464, ISBN 978-1-4673-7791-1
Editore: IEEE
DOI: 10.1109/iecbes.2016.7843493

Administration of the State Information System of the Estonian eGovernment

Autori: Ahto Kalja, Tarmo Robal, Triin Gailan
Pubblicato in: 2017 Portland International Conference on Management of Engineering and Technology (PICMET), 2017, Pagina/e 1-7, ISBN 978-1-890843-36-6
Editore: IEEE
DOI: 10.23919/picmet.2017.8125312

An Automatic Approach to Evaluate Assertions' Quality Based on Data-Mining Metrics

Autori: Tara Ghasempouri, Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik
Pubblicato in: 2018 IEEE International Test Conference in Asia (ITC-Asia), 2018, Pagina/e 61-66, ISBN 978-1-5386-5180-3
Editore: IEEE
DOI: 10.1109/itc-asia.2018.00021

AWAIT: An Ultra-Lightweight Soft-Error Mitigation Mechanism for Network-on-Chip Links

Autori: Karl Janson, Rene Pihlak, Siavoosh Payandeh Azad, Behrad Niazmand, Gert Jervan, Jaan Raik
Pubblicato in: 2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2018, Pagina/e 1-6, ISBN 978-1-5386-7957-9
Editore: IEEE
DOI: 10.1109/recosoc.2018.8449374

Augmented Coaching Ecosystem for Non-obtrusive Adaptive Personalized Elderly Care on the basis of Cloud-Fog-Dew computing paradigm

Autori: Yu. Gordienko, S. Stirenko, O. Alienin, K. Skala, Z. Sojat, A. Rojbi, J.R. Lopez Benito, E. Artetxe Gonzalez, U. Lushchyk, L. Sajn, A. Llorente Coto, G. Jervan
Pubblicato in: 2017 40th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO), 2017, Pagina/e 359-364, ISBN 978-953-233-090-8
Editore: IEEE
DOI: 10.23919/mipro.2017.7973449

Combined pseudo-exhaustive and deterministic testing of array multipliers

Autori: Adeboye Stephen Oyeniran, Siavoosh Payandeh Azad, Raimund Ubar
Pubblicato in: 2018 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR), 2018, Pagina/e 1-6, ISBN 978-1-5386-2205-6
Editore: IEEE
DOI: 10.1109/aqtr.2018.8402708

Data type dependent energy consumption estimation

Autori: Priit Ruberg, Keijo Lass, Peeter Ellervee
Pubblicato in: 2016 IEEE Nordic Circuits and Systems Conference (NORCAS), 2016, Pagina/e 1-5, ISBN 978-1-5090-1095-0
Editore: IEEE
DOI: 10.1109/norchip.2016.7792916

Developing a data acquisition system for measuring microcontroller energy consumption using LabVIEW

Autori: Priit Ruberg, Keijo Lass, Peeter Ellervee
Pubblicato in: 2016 15th Biennial Baltic Electronics Conference (BEC), 2016, Pagina/e 123-126, ISBN 978-1-5090-1393-7
Editore: IEEE
DOI: 10.1109/bec.2016.7743744

Embedded software performance estimations at different compiler optimisation levels

Autori: Priit Ruberg, Keijo Lass, Elvar Liiv, Peeter Ellervee
Pubblicato in: 2017 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE), 2017, Pagina/e 1-6, ISBN 978-1-5386-4137-8
Editore: IEEE
DOI: 10.1109/aieee.2017.8270530

Parallel Critical Path Tracing Fault Simulation in Sequential Circuits

Autori: Jaak Kousaar, Raimund Ubar, Sergei Kostin, Sergei Devadze, Jaan Raik
Pubblicato in: "2018 25th International Conference ""Mixed Design of Integrated Circuits and System"" (MIXDES)", 2018, Pagina/e 305-310, ISBN 978-83-63578-14-5
Editore: IEEE
DOI: 10.23919/mixdes.2018.8436880

Fair and Individualized Project Teamwork Evaluation for an Engineering Course

Autori: Tarmo Robal
Pubblicato in: 2018 28th EAEEIE Annual Conference (EAEEIE), 2018, Pagina/e 1-9, ISBN 978-1-5386-7711-7
Editore: IEEE
DOI: 10.1109/eaeeie.2018.8534256

Fall detection and activity recognition system for usage in smart work-wear

Autori: Mairo Leier, Gert Jervan, Ardo Allik, Kristjan Pilt, Deniss Karai, Ivo Fridolin
Pubblicato in: 2018 16th Biennial Baltic Electronics Conference (BEC), 2018, Pagina/e 1-4, ISBN 978-1-5386-7312-6
Editore: IEEE
DOI: 10.1109/bec.2018.8600959

Conditional Fault Collapsing in Digital Circuits with Shared Structurally Synthesized BDDs

Autori: Lembit Jurimagi, Raimund Ubar
Pubblicato in: 2018 16th Biennial Baltic Electronics Conference (BEC), 2018, Pagina/e 1-4, ISBN 978-1-5386-7312-6
Editore: IEEE
DOI: 10.1109/bec.2018.8600967

Gate-level modelling of NBTI-induced delays under process variations

Autori: Thiago Copetti, Guilherme Medeiros, Leticia Bolzani Poehls, Fabian Vargas, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Raimund Ubar
Pubblicato in: 2016 17th Latin-American Test Symposium (LATS), 2016, Pagina/e 75-80, ISBN 978-1-5090-1331-9
Editore: IEEE
DOI: 10.1109/latw.2016.7483343

Guideliner - a Tool to Improve Web UI Development for Better Usability

Autori: Jevgeni Marenkov, Tarmo Robal, Ahto Kalja
Pubblicato in: Proceedings of the 8th International Conference on Web Intelligence, Mining and Semantics - WIMS '18, 2018, Pagina/e 1-9, ISBN 9781-450354899
Editore: ACM Press
DOI: 10.1145/3227609.3227667

Handling of SETs on NoC Links by Exploitation of Inherent Redundancy in Circular Input Buffers

Autori: Karl Janson, Rene Pihlak, Siavoosh Payandeh Azad, Behrad Niazmand, Gert Jervan, Jaan Raik
Pubblicato in: 2018 16th Biennial Baltic Electronics Conference (BEC), 2018, Pagina/e 1-4, ISBN 978-1-5386-7312-6
Editore: IEEE
DOI: 10.1109/bec.2018.8600989

Hardware implementation of face recognition using low precision representation

Autori: Sai Kumar Dwivedi, Siavoosh Payandeh Azad, Peeter Ellervee, Ratnakar Dash
Pubblicato in: 2016 15th Biennial Baltic Electronics Conference (BEC), 2016, Pagina/e 63-66, ISBN 978-1-5090-1393-7
Editore: IEEE
DOI: 10.1109/bec.2016.7743729

Hardware-based systems for partial sorting of streaming data

Autori: Artjom Rjabov
Pubblicato in: 2016 15th Biennial Baltic Electronics Conference (BEC), 2016, Pagina/e 59-62, ISBN 978-1-5090-1393-7
Editore: IEEE
DOI: 10.1109/bec.2016.7743728

Hierarchical temporal memory implementation on FPGA using LFSR based spatial pooler address space generator

Autori: Madis Kerner, Kalle Tammemae
Pubblicato in: 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2017, Pagina/e 92-95, ISBN 978-1-5386-0472-4
Editore: IEEE
DOI: 10.1109/ddecs.2017.7934577

Hierarchical Timing-Critical Paths Analysis in Sequential Circuits

Autori: Lembit Jurimagi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Sergei Kostin
Pubblicato in: 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2018, Pagina/e 1-6, ISBN 978-1-5386-6365-3
Editore: IEEE
DOI: 10.1109/patmos.2018.8464176

High-level modeling and testing of multiple control faults in digital systems

Autori: Artjom Jasnetski, Stephen Adeboye Oyeniran, Anton Tsertov, Mario Scholzel, Raimund Ubar
Pubblicato in: 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016, Pagina/e 1-6, ISBN 978-1-5090-2467-4
Editore: IEEE
DOI: 10.1109/ddecs.2016.7482445

High-level test data generation for software-based self-test in microprocessors

Autori: Adeboye Stephen Oyeniran, Artjom Jasnetski, Anton Tsertov, Raimund Ubar
Pubblicato in: 2017 6th Mediterranean Conference on Embedded Computing (MECO), 2017, Pagina/e 1-6, ISBN 978-1-5090-6742-8
Editore: IEEE
DOI: 10.1109/meco.2017.7977167

IEEE 1687 Compliant Ecosystem for Embedded Instrumentation Access and In-Field Health Monitoring

Autori: Anton Tsertov, Artur Jutman, Konstantin Shibin, Sergei Devadze
Pubblicato in: 2018 IEEE AUTOTESTCON, 2018, Pagina/e 1-9, ISBN 978-1-5386-5223-7
Editore: IEEE
DOI: 10.1109/autest.2018.8532559

In-Field Detection of Degradation on PCB Assembly High-Speed Buses

Autori: Sergei Odintsov
Pubblicato in: 2018 IEEE AUTOTESTCON, 2018, Pagina/e 1-6, ISBN 978-1-5386-5223-7
Editore: IEEE
DOI: 10.1109/autest.2018.8532547

Understanding MPSoCs - exploiting memory microarchitectural vulnerabilities of high performance NoC-based MPSoCs

Autori: Johanna Sepulveda, Cezar Reinbrecht, Siavoosh Payandeh Azad, Behrad Niazmand, Gert Jervan
Pubblicato in: Proceedings of the 18th International Conference on Embedded Computer Systems Architectures, Modeling, and Simulation - SAMOS '18, 2018, Pagina/e 162-166, ISBN 9781-450364942
Editore: ACM Press
DOI: 10.1145/3229631.3239367

IntelliEye - Enhancing MOOC Learners' Video Watching Experience through Real-Time Attention Tracking

Autori: Tarmo Robal, Yue Zhao, Christoph Lofi, Claudia Hauff
Pubblicato in: Proceedings of the 29th on Hypertext and Social Media - HT '18, 2018, Pagina/e 106-114, ISBN 9781-450354271
Editore: ACM Press
DOI: 10.1145/3209542.3209547

Interactions of Zynq-7000 devices with general purpose computers through PCI-express: A case study

Autori: Artjom Rjabov, Alexander Sudnitson, Valery Sklyarov, Iouliia Skliarova
Pubblicato in: 2016 18th Mediterranean Electrotechnical Conference (MELECON), 2016, Pagina/e 1-4, ISBN 978-1-5090-0058-6
Editore: IEEE
DOI: 10.1109/melcon.2016.7495400

Logic-based implementation of fault-tolerant routing in 3D network-on-chips

Autori: Behrad Niazmand, Siavoosh Payandeh Azad, Jose Flich, Jaan Raik, Gert Jervan, Thomas Hollstein
Pubblicato in: 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2016, Pagina/e 1-8, ISBN 978-1-4673-9030-9
Editore: IEEE
DOI: 10.1109/nocs.2016.7579317

Minimization of the High-Level Fault Model for Microprocessor Control Parts

Autori: Raimund Ubar, Adeboye Stephen Oyeniran, Olusiji Medaiyese
Pubblicato in: 2018 16th Biennial Baltic Electronics Conference (BEC), 2018, Pagina/e 1-4, ISBN 978-1-5386-7312-6
Editore: IEEE
DOI: 10.1109/bec.2018.8600980

Mining and modelling web user engagement: A survey on academic sites for framework establishment

Autori: Tarmo Robal, Ahto Kalja
Pubblicato in: 2016 Portland International Conference on Management of Engineering and Technology (PICMET), 2016, Pagina/e 1942-1952
Editore: IEEE
DOI: 10.1109/picmet.2016.7806759

Multiple control fault testing in digital systems with high-level decision diagrams

Autori: Raimund Ubar, Stephen Adeboye Oyeniran
Pubblicato in: 2016 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR), 2016, Pagina/e 1-6, ISBN 978-1-4673-8692-0
Editore: IEEE
DOI: 10.1109/aqtr.2016.7501287

On automatic software-based self-test program generation based on high-level decision diagrams

Autori: Artjom Jasnetski, Raimund Ubar, Anton Tsertov
Pubblicato in: 2016 17th Latin-American Test Symposium (LATS), 2016, Pagina/e 177-177, ISBN 978-1-5090-1331-9
Editore: IEEE
DOI: 10.1109/latw.2016.7483357

On coverage of timing related faults at board level

Autori: Artur Jutman, Igor Aleksejev, Sergei Devadze
Pubblicato in: 2016 21th IEEE European Test Symposium (ETS), 2016, Pagina/e 1-2, ISBN 978-1-4673-9659-2
Editore: IEEE
DOI: 10.1109/ets.2016.7519295

On-line fault classification and handling in IEEE1687 based fault management system for complex SoCs

Autori: Konstantin Shibin, Sergei Devadze, Artur Jutman
Pubblicato in: 2016 17th Latin-American Test Symposium (LATS), 2016, Pagina/e 69-74, ISBN 978-1-5090-1331-9
Editore: IEEE
DOI: 10.1109/latw.2016.7483342

Ontology Design for Automatic Evaluation of Web User Interface Usability

Autori: Tarmo Robal, Jevgeni Marenkov, Ahto Kalja
Pubblicato in: 2017 Portland International Conference on Management of Engineering and Technology (PICMET), 2017, Pagina/e 1-8, ISBN 978-1-890843-36-6
Editore: IEEE
DOI: 10.23919/picmet.2017.8125425

Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation

Autori: Adeboye Stephen Oyeniran, Siavoosh Payandeh Azad, Raimund Ubar
Pubblicato in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Pagina/e 1-5, ISBN 978-1-5386-4881-0
Editore: IEEE
DOI: 10.1109/iscas.2018.8350936

Performance estimation of embedded applications on microcontrollers

Autori: Priit Ruberg, Keijo Lass, Elvar Liiv, Peeter Ellervee
Pubblicato in: 2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2017, Pagina/e 1-6, ISBN 978-1-5386-2844-7
Editore: IEEE
DOI: 10.1109/norchip.2017.8124964

Practicing start-up culture in teaching embedded systems

Autori: Uljana Reinsalu, Siavoosh Payandeh Azad, Mairo Leier, Kalle Tammemae, Thomas Hollstein
Pubblicato in: 2016 11th European Workshop on Microelectronics Education (EWME), 2016, Pagina/e 1-6, ISBN 978-1-4673-8584-8
Editore: IEEE
DOI: 10.1109/ewme.2016.7496463

QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications

Autori: Serhiy Avramenko, Siavoosh Payandeh Azad, Stefano Esposito, Behrad Niazmand, Massimo Violante, Jaan Raik, Maksim Jenihhin
Pubblicato in: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2018, Pagina/e 67-72, ISBN 978-1-5386-5754-6
Editore: IEEE
DOI: 10.1109/ddecs.2018.00-10

RAM-based mergers for data sort and frequent item computation

Autori: Artjom Rjabov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson
Pubblicato in: 2017 40th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO), 2017, Pagina/e 176-181, ISBN 978-953-233-090-8
Editore: IEEE
DOI: 10.23919/mipro.2017.7973413

Reconfigurable systems in engineering education: Best practices and future trends

Autori: Iouliia Skliarova, Valery Sklyarov, Alexander Sudnitson, Margus Kruus
Pubblicato in: 2017 IEEE Global Engineering Education Conference (EDUCON), 2017, Pagina/e 1084-1088, ISBN 978-1-5090-5467-1
Editore: IEEE
DOI: 10.1109/educon.2017.7942983

Reliable health monitoring and fault management infrastructure based on embedded instrumentation and IEEE 1687

Autori: Artur Jutman, Konstantin Shibin, Sergei Devadze
Pubblicato in: 2016 IEEE AUTOTESTCON, 2016, Pagina/e 1-10, ISBN 978-1-5090-0790-5
Editore: IEEE
DOI: 10.1109/autest.2016.7589605

Replication-Based Deterministic Testing of 2-Dimensional Arrays with Highly Interrelated Cells

Autori: Siavoosh Payandeh Azad, Adeboye Stephen Oyeniran, Raimund Ubar
Pubblicato in: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2018, Pagina/e 21-26, ISBN 978-1-5386-5754-6
Editore: IEEE
DOI: 10.1109/ddecs.2018.00011

Scalable algorithm for structural fault collapsing in digital circuits

Autori: Raimund Ubar, Lembit Jurimagi, Elmet Orasson, Jaan Raik
Pubblicato in: 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2015, Pagina/e 171-176, ISBN 978-1-4673-9140-5
Editore: IEEE
DOI: 10.1109/vlsi-soc.2015.7314411

Self-driving car ISEAUTO for research and education

Autori: Raivo Sell, Mairo Leier, Anton Rassolkin, Juhan-Peep Ernits
Pubblicato in: 2018 19th International Conference on Research and Education in Mechatronics (REM), 2018, Pagina/e 111-116, ISBN 978-1-5386-5413-2
Editore: IEEE
DOI: 10.1109/rem.2018.8421793

SoCDep 2 : A framework for dependable task deployment on many-core systems under mixed-criticality constraints

Autori: Siavoosh Payandeh Azad, Behrad Niazmand, Peeter Ellervee, Jaan Raik, Gert Jervan, Thomas Hollstein
Pubblicato in: 2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2016, Pagina/e 1-6, ISBN 978-1-5090-2520-6
Editore: IEEE
DOI: 10.1109/recosoc.2016.7533903

Software-Level TMR Approach for On-Board Data Processing in Space Applications

Autori: Karl Janson, Carl Johann Treudler, Thomas Hollstein, Jaan Raik, Maksim Jenihhin, Goerschwin Fey
Pubblicato in: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2018, Pagina/e 147-152, ISBN 978-1-5386-5754-6
Editore: IEEE
DOI: 10.1109/ddecs.2018.00033

Standards-based tools and services for building lifelong learning pathways

Autori: C. Sgouropoulou, I. Voyiatzis, A. Koutoumanos, S. Hamdioui, P. Pouyan, M. Comte, P. Prinetto, G. Airo Farulla, P. Ellervee, C. Delgado Kloos, R. Crespo Garcia
Pubblicato in: 2017 IEEE Global Engineering Education Conference (EDUCON), 2017, Pagina/e 1619-1621, ISBN 978-1-5090-5467-1
Editore: IEEE
DOI: 10.1109/educon.2017.7943065

Stationary vs. Non-stationary Mobile Learning in MOOCs

Autori: Yue Zhao, Tarmo Robal, Christoph Lofi, Claudia Hauff
Pubblicato in: Adjunct Publication of the 26th Conference on User Modeling, Adaptation and Personalization - UMAP '18, 2018, Pagina/e 299-303, ISBN 9781-450357845
Editore: ACM Press
DOI: 10.1145/3213586.3225241

Timing-critical path analysis with structurally synthesized BDDs

Autori: Raimund Ubar, Lembit Jurimagi, Maksim Jenihhin, Jaan Raik, Niyi-Leigh Olugbenga, Vladimir Viies
Pubblicato in: 2018 7th Mediterranean Conference on Embedded Computing (MECO), 2018, Pagina/e 1-6, ISBN 978-1-5386-5683-9
Editore: IEEE
DOI: 10.1109/meco.2018.8406051

TransMem: A memory architecture to support dynamic remapping and parallelism in low power high performance CGRAs

Autori: Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Ahmed Hemani, Peter Ellervee
Pubblicato in: 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2016, Pagina/e 92-99, ISBN 978-1-5090-0733-2
Editore: IEEE
DOI: 10.1109/patmos.2016.7833431

Webcam-based Attention Tracking in Online Learning - A Feasibility Study

Autori: Tarmo Robal, Yue Zhao, Christoph Lofi, Claudia Hauff
Pubblicato in: Proceedings of the 2018 Conference on Human Information Interaction&Retrieval - IUI '18, 2018, Pagina/e 189-197, ISBN 9781-450349451
Editore: ACM Press
DOI: 10.1145/3172944.3172987

Universal mitigation of NBTI-induced aging by design randomization

Autori: Maksim Jenihhin, Alexander Kamkin, Zainalabedin Navabi, Somayeh Sadeghi-Kohan
Pubblicato in: 2016 IEEE East-West Design & Test Symposium (EWDTS), 2016, Pagina/e 1-5, ISBN 978-1-5090-0693-9
Editore: IEEE
DOI: 10.1109/ewdts.2016.7807635

A framework for improving web application user interfaces through immediate evaluation

Autori: Marenkov, Jevgeni; Robal, Tarmo; Kalja, Ahto
Pubblicato in: 2016
Editore: IOS Press
DOI: 10.3233/978-1-61499-714-6-283

Automated software-based self-test generation for microprocessors

Autori: Artjom Jasnetski, Raimund Ubar, Anton Tsertov
Pubblicato in: "2017 MIXDES - 24th International Conference ""Mixed Design of Integrated Circuits and Systems", 2017, Pagina/e 453-458, ISBN 978-83-63578-12-1
Editore: IEEE
DOI: 10.23919/mixdes.2017.8005252

Comparison of Predictive Equations for Basal Metabolic Rate

Autori: Allik, A.; Mägi, S.; Pilt, K.; Karai, D.; Fridolin I.; Leier, M.; Jervan, G.
Pubblicato in: 2017
Editore: Springer

Refactoring - key to success for constantly developed projects

Autori: Põld, Janari; Kalja, Ahto; Robal, Tarmo
Pubblicato in: 2017
Editore: IOS Press
DOI: 10.3233/978-1-61499-720-7-13

BASTION: Board and SoC test instrumentation for ageing and no failure found

Autori: Artur Jutman, Christophe Lotz, Erik Larsson, Matteo Sonza Reorda, Maksim Jenihhin, Jaan Raik, Hans Kerkhoff, Rene Krenz-Baath, Piet Engelke
Pubblicato in: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, Pagina/e 115-120, ISBN 978-3-9815370-8-6
Editore: IEEE
DOI: 10.23919/DATE.2017.7926968

Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs

Autori: Francesco Pellerey, Maksim Jenihhin, Giovanni Squillero, Jaan Raik, Matteo Sonza Reorda, Valentin Tihhomirov, Raimund Ubar
Pubblicato in: 2016 IEEE 25th Asian Test Symposium (ATS), 2016, Pagina/e 304-309, ISBN 978-1-5090-3809-1
Editore: IEEE
DOI: 10.1109/ATS.2016.57

Designing reliable cyber-physical systems overview associated to the special session at FDL'16

Autori: Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon Ter Braak, Sergei Devadze, Goerschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Konighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Rock, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
Pubblicato in: 2016 Forum on Specification and Design Languages (FDL), 2016, Pagina/e 1-8, ISBN 979-10-92279-17-7
Editore: IEEE
DOI: 10.1109/FDL.2016.7880382

A comprehensive methodology for stress procedures evaluation and comparison for Burn-In of automotive SoC

Autori: D. Appello, P. Bernardi, G. Giacopelli, A. Motta, A. Pagani, G. Pollaccia, C. Rabbi, M. Restifo, P. Ruberg, E. Sanchez, C.M. Villa, F. Venini
Pubblicato in: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, Pagina/e 646-649, ISBN 978-3-9815370-8-6
Editore: IEEE
DOI: 10.23919/DATE.2017.7927068

Automated minimization of concurrent online checkers for Network-on-Chips

Autori: Pietro Saltarelli, Behrad Niazmand, Ranganathan Hariharan, Jaan Raik, Gert Jervan, Thomas Hollstein
Pubblicato in: 2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015, Pagina/e 1-8, ISBN 978-1-4673-7942-7
Editore: IEEE
DOI: 10.1109/ReCoSoC.2015.7238079

A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers

Autori: Pietro Saltarelli, Behrad Niazmand, Jaan Raik, Ranganathan Hariharan, Gert Jervan, Thomas Hollstein
Pubblicato in: 2015 Euromicro Conference on Digital System Design, 2015, Pagina/e 288-292, ISBN 978-1-4673-8035-5
Editore: IEEE
DOI: 10.1109/DSD.2015.15

FSMD RTL Design Manipulation for Clock Interface Abstraction

A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers

Rejuvenation of Nanoscale Logic at NBTI-Critical Paths Using Evolutionary TPG

Autori: Palermo, N.; Tihhomirov, V.; Copetti, T.S.; Jenihhin, M.; Raik, J.; Kostin, S.; Gaudesi, M.; Squillero, G.; Sonza Reorda, M.; Vargas, F.; Bolzani Poehls, L.
Pubblicato in: 16th IEEE Latin-American Test Symposium March 25 - 27, 2015, Puerto Vallarta, Mexico, 2015, Pagina/e 1-6
Editore: IEEE Computer Society Press

Scalable Algorithm for Structural Fault Collapsing in Digital Circuits

Autori: Ubar, Raimund; Jürimägi, Lembit; Orasson, Elmet; Raik, Jaan
Pubblicato in: IFIP/IEEE International Conference on Very Large Scale Integration - VLSI-SoC'2015, 2015, Pagina/e 1-6
Editore: IEEE Computer Society Press

New Fault Models and Self-Test Generation for Microprocessors using High-Level Decision Diagrams

SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic

Autori: Kostin, Sergei; Raik, Jaan; Ubar, Raimund; Jenihhin, Maksim; Copetti, Thiago; Vargas, Fabian; Bolzani Poehls, Leticia
Pubblicato in: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2015, Belgrade, Serbia, 2015, Pagina/e 1-6
Editore: IEEE Computer Society Press

SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores

Advanced Technical Education in the Age of Cyber Physical Systems

Autori: Vierhaus, Heinrich; Raik, Jaan; Ubar, Raimund
Pubblicato in: Proceedings of the 10th European Workshop on Microelectronics Education – EWME, 2014, Pagina/e 1-4
Editore: IEEE Computer Society

Abstraction of clock interface for conversion of RTL VHDL to SystemC

Critical Path Tracing based Simulation of Transition Delay Faults

Autori: Kõusaar, J.; Ubar, R.; Devadze, S.; Raik, J.
Pubblicato in: 17th Euromicro Conference on Digital System Design, Verona, Italy, August 27-29, 2014, 2014
Editore: IEEE Computer Society

Diagnostic Test Generation for Statistical Bug Localization using Evolutionary Computation

Assessment of diagnostic test for automated bug localization

Extended Checkers for Logic-Based Distributed Routing in Network-on-Chips

Extensible Open-Source Framework for Translating RTL VHDL IP Cores to SystemC

Autori: Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan
Pubblicato in: 15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Karlovy Vary, Czech Republic, April 8-10, 2013, 2013, Pagina/e 112-115
Editore: IEEE

At-speed self-testing of high-performance pipe-lined processing architectures

Autori: Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min
Pubblicato in: 2013 NORCHIP, 2013, Pagina/e 1-6, ISBN 978-1-4799-1647-4
Editore: IEEE
DOI: 10.1109/NORCHIP.2013.6702000

Performance Analysis of Cosimulating Processor Core in VHDL and SystemC

Autori: Syed, Saif Abrar; Shyam, Kiran A.; Jenihhin, Maksim; Raik, Jaan; Babu, C.
Pubblicato in: Proc. of 2nd IEEE International Conference on Advances in Computing, Communications & Informatics, 2013, Pagina/e 1-6
Editore: IEEE

Identifying NBTI-Critical Paths in Nanoscale Logic

Synthesis of Multiple Fault Oriented Test Groups from Single Fault Test Sets

Autori: Ubar, Raimund; Kostin, Sergei; Raik, Jaan
Pubblicato in: 8th Int. Conference on Design & Technology of Integrated Systems in Nanoscale Era - DTIS’13, 2013, Pagina/e 1-6
Editore: IEEE Computer Society

Extensible Open-Source Framework for Translating RTL VHDL IP Cores to SystemC

At-speed self-testing of high-performance pipe-lined processing architectures

Advanced Technical Education in the Age of Cyber Physical Systems

Rejuvenation of Nanoscale Logic at NBTI-Critical Paths Using Evolutionary TPG

A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers

Automated minimization of concurrent online checkers for Network-on-Chips

Performance Analysis of Cosimulating Processor Core in VHDL and SystemC

SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic

Scalable Algorithm for Structural Fault Collapsing in Digital Circuits

Synthesis of Multiple Fault Oriented Test Groups from Single Fault Test Sets

Functional self-test of high-performance pipe-lined signal processing architectures

Autori: Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min
Pubblicato in: Microprocessors and Microsystems, Numero 39/8, 2015, Pagina/e 909-918, ISSN 0141-9331
Editore: Elsevier BV
DOI: 10.1016/j.micpro.2014.11.002

Automated Design Error Localization in RTL Designs

Autori: Maksim Jenihhin, Anton Tsepurov, Valentin Tihhomirov, Jaan Raik, Hanno Hantson, Raimund Ubar, Gunter Bartsch, JorgeHernan Meza Escobar, Heinz-Dietrich Wuttke
Pubblicato in: IEEE Design & Test, Numero 31/1, 2014, Pagina/e 83-92, ISSN 2168-2356
Editore: IEEE Computer Society
DOI: 10.1109/MDAT.2013.2271420

Automated design error debug using high-level decision diagrams and mutation operators

Autori: Jaan Raik, Urmas Repinski, Anton Chepurov, Hanno Hantson, Raimund Ubar, Maksim Jenihhin
Pubblicato in: Microprocessors and Microsystems, Numero 37/4-5, 2013, Pagina/e 505-513, ISSN 0141-9331
Editore: Elsevier BV
DOI: 10.1016/j.micpro.2012.11.004

Fast identification of true critical paths in sequential circuits

Autori: Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Lembit Jürimägi
Pubblicato in: Microelectronics Reliability, Numero 81, 2018, Pagina/e 252-261, ISSN 0026-2714
Editore: Elsevier BV
DOI: 10.1016/j.microrel.2017.11.027

Modeling and simulation of circuits with shared structurally synthesized BDDs

Autori: Raimund Ubar, Lembit Jürimägi, Jaan Raik, Vladimir Viies
Pubblicato in: Microprocessors and Microsystems, Numero 48, 2017, Pagina/e 56-61, ISSN 0141-9331
Editore: Elsevier BV
DOI: 10.1016/j.micpro.2016.09.006

Health Management for Self-Aware SoCs Based on IEEE 1687 Infrastructure

Autori: Konstantin Shibin, Sergei Devadze, Artur Jutman, Martin Grabmann, Robin Pricken
Pubblicato in: IEEE Design & Test, Numero 34/6, 2017, Pagina/e 27-35, ISSN 2168-2356
Editore: IEEE Computer Society
DOI: 10.1109/MDAT.2017.2750902

Run-time reconfigurable instruments for advanced board-level testing

Autori: Igor Aleksejev, Artur Jutman, Sergei Devadze
Pubblicato in: IEEE Instrumentation & Measurement Magazine, Numero 20/4, 2017, Pagina/e 23-30, ISSN 1094-6969
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/MIM.2017.8006390

Computing Sorted Subsets for Data Processing in Communicating Software/Hardware Control Systems

Autori: Valery Sklyarov, Iouliia Skliarova, Artjom Rjabov, Alexander Sudnitson
Pubblicato in: International Journal of Computers Communications & Control, Numero 11/1, 2015, Pagina/e 126, ISSN 1841-9836
Editore: Agora University
DOI: 10.15837/ijccc.2016.1.1442

Fast Data Sort based on Searching Networks with Ring Pipeline

Autori: Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson
Pubblicato in: Elektronika ir Elektrotechnika, Numero 22/4, 2016, ISSN 1392-1215
Editore: Kauno Technologijos Universitetas
DOI: 10.5755/j01.eie.22.4.15920

Fast iterative circuits and RAM-based mergers to accelerate data sort in software/hardware systems

Autori: V Sklyarov, I Skliarova, A Rjabov, A Sudnitson
Pubblicato in: Proceedings of the Estonian Academy of Sciences, Numero 66/3, 2017, Pagina/e 323, ISSN 1736-6046
Editore: Estonian Academy Publishers
DOI: 10.3176/proc.2017.3.07

Guest Editorial: Implementation Issues in System-on-Chip

Autori: Peeter Ellervee, Jari Nurmi
Pubblicato in: Journal of Signal Processing Systems, Numero 87/3, 2017, Pagina/e 269-270, ISSN 1939-8018
Editore: Springer Verlag
DOI: 10.1007/s11265-017-1242-x

Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures

Autori: Igor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin
Pubblicato in: Journal of Electronic Testing, Numero 32/3, 2016, Pagina/e 245-255, ISSN 0923-8174
Editore: Kluwer Academic Publishers
DOI: 10.1007/s10836-016-5588-y

Polymorphic Configuration Architecture for CGRAs

Autori: Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Ahmed Hemani, Kolin Paul, Juha Plosila, Peeter Ellervee, Hannu Tenuhnen
Pubblicato in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Numero 24/1, 2016, Pagina/e 403-407, ISSN 1063-8210
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tvlsi.2015.2402392

Surrogate Data Method Requires End-Matched Segmentation of Electroencephalographic Signals to Estimate Non-linearity

Autori: Laura Päeske, Maie Bachmann, Toomas Põld, Sara Pereira Mendes de Oliveira, Jaanus Lass, Jaan Raik, Hiie Hinrikus
Pubblicato in: Frontiers in Physiology, Numero 9, 2018, ISSN 1664-042X
Editore: Frontiers Research Foundation
DOI: 10.3389/fphys.2018.01350

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

Autori: Maksim Jenihhin, Giovanni Squillero, Thiago Santos Copetti, Valentin Tihhomirov, Sergei Kostin, Marco Gaudesi, Fabian Vargas, Jaan Raik, Matteo Sonza Reorda, Leticia Bolzani Poehls, Raimund Ubar, Guilherme Cardoso Medeiros
Pubblicato in: Journal of Electronic Testing, Numero 32/3, 2016, Pagina/e 273-289, ISSN 0923-8174
Editore: Kluwer Academic Publishers
DOI: 10.1007/s10836-016-5589-x

Functional self-test of high-performance pipe-lined signal processing architectures

Autori: Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min
Pubblicato in: Microprocessors and Microsystems, Numero 01419331, 2015, Pagina/e 909-918, ISSN 0141-9331
Editore: Elsevier BV
DOI: 10.1016/j.micpro.2014.11.002

Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra

Autori: Jaak Kõusaar, Raimund Ubar, Sergei Devadze, Jaan Raik
Pubblicato in: Microprocessors and Microsystems, Numero 01419331, 2015, Pagina/e 1130-1138, ISSN 0141-9331
Editore: Elsevier BV
DOI: 10.1016/j.micpro.2015.05.003

Automated Design Error Localization in RTL Designs

Autori: Maksim Jenihhin, Anton Tsepurov, Valentin Tihhomirov, Jaan Raik, Hanno Hantson, Raimund Ubar, Gunter Bartsch, JorgeHernan Meza Escobar, Heinz-Dietrich Wuttke
Pubblicato in: IEEE Design & Test, Numero 21682356, 2014, Pagina/e 83-92, ISSN 2168-2356
Editore: IEEE Computer Society
DOI: 10.1109/MDAT.2013.2271420

Automated design error debug using high-level decision diagrams and mutation operators

Autori: Jaan Raik, Urmas Repinski, Anton Chepurov, Hanno Hantson, Raimund Ubar, Maksim Jenihhin
Pubblicato in: Microprocessors and Microsystems, Numero 01419331, 2013, Pagina/e 505-513, ISSN 0141-9331
Editore: Elsevier BV
DOI: 10.1016/j.micpro.2012.11.004

Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra

Autori: Jaak Kõusaar, Raimund Ubar, Sergei Devadze, Jaan Raik
Pubblicato in: Microprocessors and Microsystems, Numero 39/8, 2015, Pagina/e 1130-1138, ISSN 0141-9331
Editore: Elsevier BV
DOI: 10.1016/j.micpro.2015.05.003

Designing Reliable Cyber-Physical Systems

Autori: Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Goerschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Shlomit Koyfman, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
Pubblicato in: Lecture Notes in Electrical Engineering, 2018, Pagina/e 15-38
Editore: Springer International Publishing
DOI: 10.1007/978-3-319-62920-9_2

A Study on Immediate Automatic Usability Evaluation of Web Application User Interfaces

Autori: Jevgeni Marenkov, Tarmo Robal, Ahto Kalja
Pubblicato in: Databases and Information Systems, Numero 615, 2016, Pagina/e 257-271, ISBN 978-3-319-40179-9
Editore: Springer International Publishing
DOI: 10.1007/978-3-319-40180-5_18

A Tool for Design-Time Usability Evaluation of Web User Interfaces

Autori: Jevgeni Marenkov, Tarmo Robal, Ahto Kalja
Pubblicato in: Advances in Databases and Information Systems, Numero 10509, 2017, Pagina/e 394-407, ISBN 978-3-319-66916-8
Editore: Springer International Publishing
DOI: 10.1007/978-3-319-66917-5_26

Can I Have a Mooc2Go, Please? On the Viability of Mobile vs. Stationary Learning

Autori: Yue Zhao, Tarmo Robal, Christoph Lofi, Claudia Hauff
Pubblicato in: Lifelong Technology-Enhanced Learning - 13th European Conference on Technology Enhanced Learning, EC-TEL 2018, Leeds, UK, September 3-5, 2018, Proceedings, Numero 11082, 2018, Pagina/e 101-115, ISBN 978-3-319-98571-8
Editore: Springer International Publishing
DOI: 10.1007/978-3-319-98572-5_8

Classification Algorithm Improvement for Physical Activity Recognition in Maritime Environments

Autori: Ardo Allik, Kristjan Pilt, Deniss Karai, Ivo Fridolin, Mairo Leier, Gert Jervan
Pubblicato in: World Congress on Medical Physics and Biomedical Engineering 2018, Numero 68/3, 2019, Pagina/e 13-17, ISBN 978-981-10-9022-6
Editore: Springer Singapore
DOI: 10.1007/978-981-10-9023-3_3

EEG Functional Connectivity Detects Seasonal Changes

Autori: Laura Päeske, Maie Bachmann, Jaan Raik, Hiie Hinrikus
Pubblicato in: World Congress on Medical Physics and Biomedical Engineering 2018 - June 3-8, 2018, Prague, Czech Republic (Vol.2), Numero 68/2, 2019, Pagina/e 237-240, ISBN 978-981-10-9037-0
Editore: Springer Singapore
DOI: 10.1007/978-981-10-9038-7_44

Energy-Efficient Multi-fragment Markov Model Guided Online Model-Based Testing for MPSoC

Autori: Jüri Vain, Leonidas Tsiopoulos, Vyacheslav Kharchenko, Apneet Kaur, Maksim Jenihhin, Jaan Raik, Sven Nõmm
Pubblicato in: Green IT Engineering: Social, Business and Industrial Applications, Numero 171, 2019, Pagina/e 273-297, ISBN 978-3-030-00252-7
Editore: Springer International Publishing
DOI: 10.1007/978-3-030-00253-4_12

Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs

Autori: Raimund Ubar, Lembit Jürimägi, Elmet Orasson, Jaan Raik
Pubblicato in: VLSI-SoC: Design for Reliability, Security, and Low Power, Numero 483, 2016, Pagina/e 23-45, ISBN 978-3-319-46096-3
Editore: Springer International Publishing
DOI: 10.1007/978-3-319-46097-0_2

Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation

Autori: Marco Gaudesi, Maksim Jenihhin, Jaan Raik, Ernesto Sanchez, Giovanni Squillero, Valentin Tihhomirov, Raimund Ubar
Pubblicato in: Applications of Evolutionary Computation, 2014, Pagina/e 425-436, ISBN 978-3-662-45523-4
Editore: Springer Berlin Heidelberg
DOI: 10.1007/978-3-662-45523-4_35

Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation

Design-Time Web Usability Evaluation with Guideliner

Autori: Jevgeni Marenkov, Tarmo Robal, Ahto Kalja
Pubblicato in: Complex Systems Informatics and Modeling Quarterly, Numero 15, 2018, Pagina/e 90-109, ISSN 2255-9922
Editore: 0302-9743
DOI: 10.7250/csimq.2018-15.05

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