Ultra-Low PoweR technologIes and MEmory architectures for IoT

Informazioni relative al progetto

PRIME

ID dell’accordo di sovvenzione: 692519

DOI

10.3030/692519

Progetto chiuso

Data della firma CE 4 Maggio 2016

Data di avvio 1 Dicembre 2015

Data di completamento 30 Settembre 2019

Finanziato da

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Costo totale

€ 38 296 264,00

Contributo UE

€ 12 038 776,58

Coordinato da

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM
Belgium

CORDIS fornisce collegamenti ai risultati finali pubblici e alle pubblicazioni dei progetti ORIZZONTE.

I link ai risultati e alle pubblicazioni dei progetti del 7° PQ, così come i link ad alcuni tipi di risultati specifici come dataset e software, sono recuperati dinamicamente da .OpenAIRE .

Risultati finali

Other (2)

Web page
Public communication of final result

Pubblicazioni

Peer reviewed articles (5)

Barrier breakdown mechanism in nano-scale perpendicular magnetic tunnel junctions with ultrathin MgO barrier

Autori: Hua Lv, Diana C. Leitao, Zhiwei Hou, Paulo P. Freitas, Susana Cardoso, Thomas Kämpfe, Johannes Müller, Juergen Langer, Jerzy Wrona
Pubblicato in: AIP Advances, Numero 8/5, 2018, Pagina/e 055908, ISSN 2158-3226
Editore: American Institute of Physics Inc.
DOI: 10.1063/1.5007656

The annealing effect on memory state stability and interlayer coupling in perpendicular magnetic tunnel junctions with ultrathin MgO barrier

Autori: Hua Lv, João Fidalgo, Diana C. Leitão, Ana V. Silva, Thomas Kämpfe, Stefan Riedel, Juergen Langer, Jerzy Wrona, Berthold Ocker, Paulo P. Freitas, Susana Cardoso
Pubblicato in: Journal of Magnetism and Magnetic Materials, Numero 477, 2019, Pagina/e 142-146, ISSN 0304-8853
Editore: Elsevier BV
DOI: 10.1016/j.jmmm.2019.01.050

Pulse mode of operation – A new booster of TEG, improving power up to X2.7 – to better fit IoT requirements

Autori: Maciej Haras, Michał Markiewicz, Stéphane Monfray, Thomas Skotnicki
Pubblicato in: Nano Energy, Numero In Press, 2019, Pagina/e 104204, ISSN 2211-2855
Editore: Elsevier BV
DOI: 10.1016/j.nanoen.2019.104204

Advanced FD-SOI and Beyond Low Temperature SmartCut™ Enables High Density 3-D SoC Applications

Autori: W. Schwarzenbach, B.-Y. Nguyen, L. Ecarnot, S. Loubriat, M. Detard, E. Cela, C. Bertrand-Giuliani, G. Chabanne, C. Maddalon, N. Daval, C. Maleville
Pubblicato in: IEEE Journal of the Electron Devices Society, Numero 7, 2019, Pagina/e 863-868, ISSN 2168-6734
Editore: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/jeds.2019.2916460

Slicing FIFOs for On-Chip Memory Bandwidth Exhaustion

Autori: Mattis Hasler, Robert Wittig, Emil Matus, Gerhard Fettweis
Pubblicato in: IEEE Transactions on Circuits and Systems I: Regular Papers, Numero Print ISSN: 1549-8328 Electronic ISSN: 1558-0806, 2019, Pagina/e 1-10, ISSN 1549-8328
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcsi.2019.2926134

Conference proceedings (21)

Down to 15nm BOX: SOI extendability for planar fully depleted application beyond 22FD

Autori: W. Schwarzenbach, F. Allibert, C. Le Royer, L. Grenouillet, C. Malaquin, C. Bertrand-Giuliani, F. Boedt, S. Loubriat, C. Michau, D. Parissi, B.-Y. Nguyen
Pubblicato in: 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016, Pagina/e 1-2, ISBN 978-1-5090-4391-0
Editore: IEEE
DOI: 10.1109/S3S.2016.7804377

Combined TDM and SDM Circuit Switching NoCs with Dedicated Connection Allocator

Autori: Yong Chen, Emil Matus, Gerhard P. Fettweis
Pubblicato in: 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, Pagina/e 104-109, ISBN 978-1-5090-6762-6
Editore: IEEE
DOI: 10.1109/ISVLSI.2017.27

Combined packet and TDM circuit switching NoCs with novel connection configuration mechanism

Autori: Yong Chen, Emil Matus, Gerhard P. Fettweis
Pubblicato in: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, Pagina/e 1-4, ISBN 978-1-4673-6853-7
Editore: IEEE
DOI: 10.1109/ISCAS.2017.8050829

A fixed point exponential function accelerator for a neuromorphic many-core system

Autori: Johannes Partzsch, Sebastian Hoppner, Matthias Eberlein, Rene Schuffny, Christian Mayr, David R. Lester, Steve Furber
Pubblicato in: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, Pagina/e 1-4, ISBN 978-1-4673-6853-7
Editore: IEEE
DOI: 10.1109/ISCAS.2017.8050528

Dynamic voltage and frequency scaling for neuromorphic many-core systems

Autori: Sebastian Hoppner, Yexin Yan, Bernhard Vogginger, Andreas Dixius, Johannes Partzsch, Felix Neumarker, Stephan Hartmann, Stefan Schiefer, Stefan Scholze, Georg Ellguth, Love Cederstroem, Matthias Eberlein, Christian Mayr, Steve Temple, Luis Plana, Jim Garside, Simon Davison, David R. Lester, Steve Furber
Pubblicato in: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, Pagina/e 1-4, ISBN 978-1-4673-6853-7
Editore: IEEE
DOI: 10.1109/ISCAS.2017.8050656

MESH: Explicit and flexible generation of analog arrays

Autori: Benjamin Prautsch, Uwe Eichler, Torsten Reich, Jens Lienig
Pubblicato in: 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017, Pagina/e 1-4, ISBN 978-1-5090-5052-9
Editore: IEEE
DOI: 10.1109/SMACD.2017.7981572

Dynamic body bias for 22 nm FD-SOI CMOS Technology

Autori: Nedelcu, Stefan; Voelker, Matthias; Klein, Leonhard; Schuhmann, Claudia; Schuhmann, Norbert; Hauer, Johann; Reich, Torsten; Rao, Sunil
Pubblicato in: 15. ITG/GMM-Symposium ANALOG 2016, Numero 15. ITG/GMM-Symposium ANALOG 2016, 2016, ISBN 978-3-8007-4265-3
Editore: IEEE

Modeling and design considerations for negative capacitance field-effect transistors

Autori: Michael Hoffmann, Milan Pesic, Stefan Slesazeck, Uwe Schroeder, Thomas Mikolajick, Thomas Mikolajick
Pubblicato in: 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Numero 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017, Pagina/e 1-4, ISBN 978-1-5090-5313-1
Editore: IEEE
DOI: 10.1109/ulis.2017.7962577

Ultra-Low-Power SAR ADC In 22 Nm FD-SOI Technology Using Body-Biasing

Autori: Jotschke, Marcel; Rao, Sunil Satish; Prautsch, Benjamin; Reich, Torsten
Pubblicato in: Semiconductor Engineering, 2019, ISBN 978-3-8007-4754-2
Editore: Semiconductor Engineering

Energy-Efficient Hash Join Implementations in Hardware-Accelerated MPSoCs

Autori: S Haas, G Fettweis
Pubblicato in: Eighth International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, Numero Eighth International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, 2017
Editore: adms

A Hybrid Execution Approach to Improve the Performance of Dataflow Applications

Autori: M Hasler, R Wittig, E Matus, G Fettweis
Pubblicato in: 16th International SoC Design Conference, 2019
Editore: 16th International SoC Design Conference

Statistical Access Interval Prediction for Tightly Coupled Memory Systems

Autori: Robert Wittig, Mattis Hasler, Emil Matus, Gerhard Fettweis
Pubblicato in: 2019 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), Numero Annually, 2019, Pagina/e 1-3, ISBN 978-1-7281-1749-2
Editore: IEEE
DOI: 10.1109/coolchips.2019.8721304

A low-power BLE transceiver with support for phase-based ranging, featuring 5μs PLL locking time and 5.3ms ranging time, enabled by staircase-chirp PLL with sticky-lock channel-switching

Autori: Elbert Bechthum, Johan Dijkhuis, Ming Ding, Yuming He, Johan van den Heuvel, Paul Mateman, Gert-Jan van Schaik, Kenichi Shibata*, Minyoung Song, Evgenii Tiurin, Stefano Traferro, Nick Winkel, Yao-Hong Li, Christian Bachmann
Pubblicato in: 2020 International Solid-State Circuits Conference, 2020
Editore: 2020 International Solid-State Circuits Conference

Gewitter im Chip - Resistive Speicher für low-power Anwendungen (Chip-internal thunderstorm - resistive memories for low power applications)

Autori: Drescher, Maximilian; Erben, Elke; Grass, Carsten; Trentzsch, Martin; Lazarevic, Florian; Leitsmann, Roman; Plaenitz, Philipp; Mchedlidze, Teimuraz; Seidel, Konrad; Liske, Romy; Bartha, Johann Wolfgang
Pubblicato in: MikroSystemTechnik Kongress 2017, Numero MikroSystemTechnik Kongress 2017, 2017, Pagina/e pp.774-776, ISBN 978-3-8007-4491-6
Editore: MikroSystemTechnik Kongress 2017

Beyond advanced FDSOI: Low Temp SmartCut for enabling High Density 3D SoC applications

Autori: W. Schwarzenbach, B. -Y. Nguyen, L. Ecarnot, S. Loubriat, M. Detard, E. Cela, C. Bertrand-Giuliani, G. Chabanne, C. Maddalon, N. Daval, C. Girard, C. Maleville
Pubblicato in: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Numero annually, 2018, Pagina/e 1-2, ISBN 978-1-5386-7627-1
Editore: IEEE
DOI: 10.1109/s3s.2018.8640192

Application Specific Instruction Processor for Dynamic Connection Allocation in TDM-NoCs

Autori: S Nam, E Matus, G Fettweis
Pubblicato in: 32th IEEE International System-On-Chip Conference, 2019
Editore: IEEE

Queue Based Memory Management Unit for Heterogeneous MPSoCs

Autori: Robert Wittig, Mattis Hasler, Emil Matus, Gerhard Fettweis
Pubblicato in: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), Numero annually, 2019, Pagina/e 1297-1300, ISBN 978-3-9819263-2-3
Editore: IEEE
DOI: 10.23919/date.2019.8715129

Charakterisierung der Zuverlässigkeit in der High-k Metal Gate Technologie (Reliability characterization in High-k metal gate technology)

Autori: Seidel, Konrad; Riedel, Stefan; Kalishettyhalli Ma, Mamathamba; Polakowski, Patrick; Müller, Johannes
Pubblicato in: MikroSystemTechnik Kongress 2017, Numero MikroSystemTechnik Kongress 2017, 2017, Pagina/e pp.488-491, ISBN 978-3-8007-4491-6
Editore: MikroSystemTechnik Kongress 2017

HW/SW-database-codesign for compressed bitmap index processing

Autori: Sebastian Haas, Tomas Karnagel, Oliver Arnold, Erik Laux, Benjamin Schlegel, Gerhard Fettweis, Wolfgang Lehner
Pubblicato in: 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Numero annually, 2016, Pagina/e 50-57, ISBN 978-1-5090-1503-0
Editore: IEEE
DOI: 10.1109/ASAP.2016.7760772

MESH: Explicit and Flexible Generation of Analog Arrays

Autori: Benjamin Prautsch, Uwe Eichler, Torsten Reich, Jens Lienig
Pubblicato in: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Numero annually, 2017
Editore: IEEE

Body biasing for analog design: Practical experiences in 22 nm FD-SOI

Autori: Sunil Satish Rao, Benjamin Prautsch, Ashish Shrivastava, Torsten Reich
Pubblicato in: 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Numero annually, 2017, Pagina/e 73-78, ISBN 978-1-5386-0472-4
Editore: IEEE
DOI: 10.1109/DDECS.2017.7934580

Thesis and dissertations (1)

PVD and ALD process development of advanced oxide-based RRAM-stacks

Autori: Kalishetthyhalli Mahadevaiah, Mamathamba
Pubblicato in: 2017
Editore: Fraunhofer

Diritti di proprietà intellettuale

Patent (7)

Circuit for symbol timing synchronization

Numero candidatura/pubblicazione: 14 153485
Data: 2014-01-31
Candidato/i: STICHTING IMEC NEDERLAND

PHASE TRACKING RECEIVER

Numero candidatura/pubblicazione: 15 201303
Data: 2015-12-18
Candidato/i: STICHTING IMEC NEDERLAND

RECEIVER FOR FREQUENCY OFFSET CORRECTION

Numero candidatura/pubblicazione: 16 169134
Data: 2016-05-11
Candidato/i: STICHTING IMEC NEDERLAND

DIGITAL PHASE LOCKED LOOP AND METHOD FOR OPERATING THE SAME

Numero candidatura/pubblicazione: 16 186301
Data: 2016-08-30
Candidato/i: STICHTING IMEC NEDERLAND

MEMORY UNIT

Numero candidatura/pubblicazione: 20 17051593
Data: 2017-06-02
Candidato/i: SURECORE LTD

METHOD FOR DISTANCE DETERMINATION

Numero candidatura/pubblicazione: 17 209014
Data: 2017-12-20
Candidato/i: STICHTING IMEC NEDERLAND

METHOD TO REDUCE AGING OF A CACHE MEMORY

Numero candidatura/pubblicazione: 18 175173
Data: 2018-05-30
Candidato/i: INTRINSIC ID BV