Ultra-Low PoweR technologIes and MEmory architectures for IoT

Información del proyecto

PRIME

Identificador del acuerdo de subvención: 692519

DOI

10.3030/692519

Proyecto cerrado

Fecha de la firma de la CE 4 Mayo 2016

Fecha de inicio 1 Diciembre 2015

Fecha de finalización 30 Septiembre 2019

Financiado con arreglo a

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Coste total

€ 38 296 264,00

Aportación de la UE

€ 12 038 776,58

Coordinado por

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM
Belgium

CORDIS proporciona enlaces a los documentos públicos y las publicaciones de los proyectos de los programas marco HORIZONTE.

Los enlaces a los documentos y las publicaciones de los proyectos del Séptimo Programa Marco, así como los enlaces a algunos tipos de resultados específicos, como conjuntos de datos y «software», se obtienen dinámicamente de OpenAIRE .

Resultado final

Other (2)

Web page
Public communication of final result

Publicaciones

Peer reviewed articles (5)

Barrier breakdown mechanism in nano-scale perpendicular magnetic tunnel junctions with ultrathin MgO barrier

Autores: Hua Lv, Diana C. Leitao, Zhiwei Hou, Paulo P. Freitas, Susana Cardoso, Thomas Kämpfe, Johannes Müller, Juergen Langer, Jerzy Wrona
Publicado en: AIP Advances, Edición 8/5, 2018, Página(s) 055908, ISSN 2158-3226
Editor: American Institute of Physics Inc.
DOI: 10.1063/1.5007656

The annealing effect on memory state stability and interlayer coupling in perpendicular magnetic tunnel junctions with ultrathin MgO barrier

Autores: Hua Lv, João Fidalgo, Diana C. Leitão, Ana V. Silva, Thomas Kämpfe, Stefan Riedel, Juergen Langer, Jerzy Wrona, Berthold Ocker, Paulo P. Freitas, Susana Cardoso
Publicado en: Journal of Magnetism and Magnetic Materials, Edición 477, 2019, Página(s) 142-146, ISSN 0304-8853
Editor: Elsevier BV
DOI: 10.1016/j.jmmm.2019.01.050

Pulse mode of operation – A new booster of TEG, improving power up to X2.7 – to better fit IoT requirements

Autores: Maciej Haras, Michał Markiewicz, Stéphane Monfray, Thomas Skotnicki
Publicado en: Nano Energy, Edición In Press, 2019, Página(s) 104204, ISSN 2211-2855
Editor: Elsevier BV
DOI: 10.1016/j.nanoen.2019.104204

Advanced FD-SOI and Beyond Low Temperature SmartCut™ Enables High Density 3-D SoC Applications

Autores: W. Schwarzenbach, B.-Y. Nguyen, L. Ecarnot, S. Loubriat, M. Detard, E. Cela, C. Bertrand-Giuliani, G. Chabanne, C. Maddalon, N. Daval, C. Maleville
Publicado en: IEEE Journal of the Electron Devices Society, Edición 7, 2019, Página(s) 863-868, ISSN 2168-6734
Editor: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/jeds.2019.2916460

Slicing FIFOs for On-Chip Memory Bandwidth Exhaustion

Autores: Mattis Hasler, Robert Wittig, Emil Matus, Gerhard Fettweis
Publicado en: IEEE Transactions on Circuits and Systems I: Regular Papers, Edición Print ISSN: 1549-8328 Electronic ISSN: 1558-0806, 2019, Página(s) 1-10, ISSN 1549-8328
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcsi.2019.2926134

Conference proceedings (21)

Down to 15nm BOX: SOI extendability for planar fully depleted application beyond 22FD

Autores: W. Schwarzenbach, F. Allibert, C. Le Royer, L. Grenouillet, C. Malaquin, C. Bertrand-Giuliani, F. Boedt, S. Loubriat, C. Michau, D. Parissi, B.-Y. Nguyen
Publicado en: 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016, Página(s) 1-2, ISBN 978-1-5090-4391-0
Editor: IEEE
DOI: 10.1109/S3S.2016.7804377

Combined TDM and SDM Circuit Switching NoCs with Dedicated Connection Allocator

Autores: Yong Chen, Emil Matus, Gerhard P. Fettweis
Publicado en: 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, Página(s) 104-109, ISBN 978-1-5090-6762-6
Editor: IEEE
DOI: 10.1109/ISVLSI.2017.27

Combined packet and TDM circuit switching NoCs with novel connection configuration mechanism

Autores: Yong Chen, Emil Matus, Gerhard P. Fettweis
Publicado en: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, Página(s) 1-4, ISBN 978-1-4673-6853-7
Editor: IEEE
DOI: 10.1109/ISCAS.2017.8050829

A fixed point exponential function accelerator for a neuromorphic many-core system

Autores: Johannes Partzsch, Sebastian Hoppner, Matthias Eberlein, Rene Schuffny, Christian Mayr, David R. Lester, Steve Furber
Publicado en: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, Página(s) 1-4, ISBN 978-1-4673-6853-7
Editor: IEEE
DOI: 10.1109/ISCAS.2017.8050528

Dynamic voltage and frequency scaling for neuromorphic many-core systems

Autores: Sebastian Hoppner, Yexin Yan, Bernhard Vogginger, Andreas Dixius, Johannes Partzsch, Felix Neumarker, Stephan Hartmann, Stefan Schiefer, Stefan Scholze, Georg Ellguth, Love Cederstroem, Matthias Eberlein, Christian Mayr, Steve Temple, Luis Plana, Jim Garside, Simon Davison, David R. Lester, Steve Furber
Publicado en: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, Página(s) 1-4, ISBN 978-1-4673-6853-7
Editor: IEEE
DOI: 10.1109/ISCAS.2017.8050656

MESH: Explicit and flexible generation of analog arrays

Autores: Benjamin Prautsch, Uwe Eichler, Torsten Reich, Jens Lienig
Publicado en: 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017, Página(s) 1-4, ISBN 978-1-5090-5052-9
Editor: IEEE
DOI: 10.1109/SMACD.2017.7981572

Dynamic body bias for 22 nm FD-SOI CMOS Technology

Autores: Nedelcu, Stefan; Voelker, Matthias; Klein, Leonhard; Schuhmann, Claudia; Schuhmann, Norbert; Hauer, Johann; Reich, Torsten; Rao, Sunil
Publicado en: 15. ITG/GMM-Symposium ANALOG 2016, Edición 15. ITG/GMM-Symposium ANALOG 2016, 2016, ISBN 978-3-8007-4265-3
Editor: IEEE

Modeling and design considerations for negative capacitance field-effect transistors

Autores: Michael Hoffmann, Milan Pesic, Stefan Slesazeck, Uwe Schroeder, Thomas Mikolajick, Thomas Mikolajick
Publicado en: 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Edición 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017, Página(s) 1-4, ISBN 978-1-5090-5313-1
Editor: IEEE
DOI: 10.1109/ulis.2017.7962577

Ultra-Low-Power SAR ADC In 22 Nm FD-SOI Technology Using Body-Biasing

Autores: Jotschke, Marcel; Rao, Sunil Satish; Prautsch, Benjamin; Reich, Torsten
Publicado en: Semiconductor Engineering, 2019, ISBN 978-3-8007-4754-2
Editor: Semiconductor Engineering

Energy-Efficient Hash Join Implementations in Hardware-Accelerated MPSoCs

Autores: S Haas, G Fettweis
Publicado en: Eighth International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, Edición Eighth International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, 2017
Editor: adms

A Hybrid Execution Approach to Improve the Performance of Dataflow Applications

Autores: M Hasler, R Wittig, E Matus, G Fettweis
Publicado en: 16th International SoC Design Conference, 2019
Editor: 16th International SoC Design Conference

Statistical Access Interval Prediction for Tightly Coupled Memory Systems

Autores: Robert Wittig, Mattis Hasler, Emil Matus, Gerhard Fettweis
Publicado en: 2019 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), Edición Annually, 2019, Página(s) 1-3, ISBN 978-1-7281-1749-2
Editor: IEEE
DOI: 10.1109/coolchips.2019.8721304

A low-power BLE transceiver with support for phase-based ranging, featuring 5μs PLL locking time and 5.3ms ranging time, enabled by staircase-chirp PLL with sticky-lock channel-switching

Autores: Elbert Bechthum, Johan Dijkhuis, Ming Ding, Yuming He, Johan van den Heuvel, Paul Mateman, Gert-Jan van Schaik, Kenichi Shibata*, Minyoung Song, Evgenii Tiurin, Stefano Traferro, Nick Winkel, Yao-Hong Li, Christian Bachmann
Publicado en: 2020 International Solid-State Circuits Conference, 2020
Editor: 2020 International Solid-State Circuits Conference

Gewitter im Chip - Resistive Speicher für low-power Anwendungen (Chip-internal thunderstorm - resistive memories for low power applications)

Autores: Drescher, Maximilian; Erben, Elke; Grass, Carsten; Trentzsch, Martin; Lazarevic, Florian; Leitsmann, Roman; Plaenitz, Philipp; Mchedlidze, Teimuraz; Seidel, Konrad; Liske, Romy; Bartha, Johann Wolfgang
Publicado en: MikroSystemTechnik Kongress 2017, Edición MikroSystemTechnik Kongress 2017, 2017, Página(s) pp.774-776, ISBN 978-3-8007-4491-6
Editor: MikroSystemTechnik Kongress 2017

Beyond advanced FDSOI: Low Temp SmartCut for enabling High Density 3D SoC applications

Autores: W. Schwarzenbach, B. -Y. Nguyen, L. Ecarnot, S. Loubriat, M. Detard, E. Cela, C. Bertrand-Giuliani, G. Chabanne, C. Maddalon, N. Daval, C. Girard, C. Maleville
Publicado en: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Edición annually, 2018, Página(s) 1-2, ISBN 978-1-5386-7627-1
Editor: IEEE
DOI: 10.1109/s3s.2018.8640192

Application Specific Instruction Processor for Dynamic Connection Allocation in TDM-NoCs

Autores: S Nam, E Matus, G Fettweis
Publicado en: 32th IEEE International System-On-Chip Conference, 2019
Editor: IEEE

Queue Based Memory Management Unit for Heterogeneous MPSoCs

Autores: Robert Wittig, Mattis Hasler, Emil Matus, Gerhard Fettweis
Publicado en: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), Edición annually, 2019, Página(s) 1297-1300, ISBN 978-3-9819263-2-3
Editor: IEEE
DOI: 10.23919/date.2019.8715129

Charakterisierung der Zuverlässigkeit in der High-k Metal Gate Technologie (Reliability characterization in High-k metal gate technology)

Autores: Seidel, Konrad; Riedel, Stefan; Kalishettyhalli Ma, Mamathamba; Polakowski, Patrick; Müller, Johannes
Publicado en: MikroSystemTechnik Kongress 2017, Edición MikroSystemTechnik Kongress 2017, 2017, Página(s) pp.488-491, ISBN 978-3-8007-4491-6
Editor: MikroSystemTechnik Kongress 2017

HW/SW-database-codesign for compressed bitmap index processing

Autores: Sebastian Haas, Tomas Karnagel, Oliver Arnold, Erik Laux, Benjamin Schlegel, Gerhard Fettweis, Wolfgang Lehner
Publicado en: 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Edición annually, 2016, Página(s) 50-57, ISBN 978-1-5090-1503-0
Editor: IEEE
DOI: 10.1109/ASAP.2016.7760772

MESH: Explicit and Flexible Generation of Analog Arrays

Autores: Benjamin Prautsch, Uwe Eichler, Torsten Reich, Jens Lienig
Publicado en: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Edición annually, 2017
Editor: IEEE

Body biasing for analog design: Practical experiences in 22 nm FD-SOI

Autores: Sunil Satish Rao, Benjamin Prautsch, Ashish Shrivastava, Torsten Reich
Publicado en: 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Edición annually, 2017, Página(s) 73-78, ISBN 978-1-5386-0472-4
Editor: IEEE
DOI: 10.1109/DDECS.2017.7934580

Thesis and dissertations (1)

PVD and ALD process development of advanced oxide-based RRAM-stacks

Autores: Kalishetthyhalli Mahadevaiah, Mamathamba
Publicado en: 2017
Editor: Fraunhofer

Derechos de propiedad intelectual

Patent (7)

Circuit for symbol timing synchronization

Número de solicitud/publicación: 14 153485
Fecha: 2014-01-31
Solicitante(s): STICHTING IMEC NEDERLAND

PHASE TRACKING RECEIVER

Número de solicitud/publicación: 15 201303
Fecha: 2015-12-18
Solicitante(s): STICHTING IMEC NEDERLAND

RECEIVER FOR FREQUENCY OFFSET CORRECTION

Número de solicitud/publicación: 16 169134
Fecha: 2016-05-11
Solicitante(s): STICHTING IMEC NEDERLAND

DIGITAL PHASE LOCKED LOOP AND METHOD FOR OPERATING THE SAME

Número de solicitud/publicación: 16 186301
Fecha: 2016-08-30
Solicitante(s): STICHTING IMEC NEDERLAND

MEMORY UNIT

Número de solicitud/publicación: 20 17051593
Fecha: 2017-06-02
Solicitante(s): SURECORE LTD

METHOD FOR DISTANCE DETERMINATION

Número de solicitud/publicación: 17 209014
Fecha: 2017-12-20
Solicitante(s): STICHTING IMEC NEDERLAND

METHOD TO REDUCE AGING OF A CACHE MEMORY

Número de solicitud/publicación: 18 175173
Fecha: 2018-05-30
Solicitante(s): INTRINSIC ID BV