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Zero damage Ultra-Low-K etch using the precursor CONDensation technique

Objective

Since the beginning of the electronic evolution, size of transistor never stops to decrease accordingly to Moore’s law. This scaling applies also to the interconnects, composed by conductor and insulating materials, leading to an overall increase of the resistivity of the conductor and the dielectric’s capacitance, ultimately causing delayed signal transmission (so-called RC delay). In order to decrease the resistivity, Al was replaced by Cu as a conductor. The circuit’s capacitance can be lowered by using materials with lower dielectric permittivity, named low-k’s. Nowadays, the most successful low-k dielectrics are porous organo-silicate glasses, with porosity up to 50%, pore size around 1.5-2 nm and k-values down to 1.8 (k=4.2 for bulk SiO2). Interconnects are nowadays built by the Damascene technique, where the dielectric is first deposited, then locally etched away, followed by metal deposition in the patterned structure and polishing for metal excess removal. Due to their intrinsic porosity, most of processing steps cause low-k damage, amongst which plasma etching is the most damaging. The present proposal aims at understanding and optimizing zero-damage cryogenic etching of low-k materials, compatible with the micro-electronics industry (at temperature above -60°C). Besides the improvement of the etching process and the better understanding of reactions damaging the low-k materials during plasma etching, this work will investigate the phenomenon of micro-capillary condensation into porous materials, which is not widely explored and can lead to other applications in micro-electronics and in other nanotechnology domains. This research project will contribute to enable the so-called 5nm node in future CMOS manufacturing, and as a consequence it will have a wide economic impact. Finally, this research will allow the applicant to extend his technical and project management skills, strengthening his profile for a future career in the semiconductor industry or R&D.

Fields of science (EuroSciVoc)

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Programme(s)

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Topic(s)

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Funding Scheme

Funding scheme (or “Type of Action”) inside a programme with common features. It specifies: the scope of what is funded; the reimbursement rate; specific evaluation criteria to qualify for funding; and the use of simplified forms of costs like lump sums.

MSCA-IF-EF-ST - Standard EF

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Call for proposal

Procedure for inviting applicants to submit project proposals, with the aim of receiving EU funding.

(opens in new window) H2020-MSCA-IF-2015

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Coordinator

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM
Net EU contribution

Net EU financial contribution. The sum of money that the participant receives, deducted by the EU contribution to its linked third party. It considers the distribution of the EU financial contribution between direct beneficiaries of the project and other types of participants, like third-party participants.

€ 160 800,00
Address
KAPELDREEF 75
3001 Leuven
Belgium

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Region
Vlaams Gewest Prov. Vlaams-Brabant Arr. Leuven
Activity type
Research Organisations
Links
Total cost

The total costs incurred by this organisation to participate in the project, including direct and indirect costs. This amount is a subset of the overall project budget.

€ 160 800,00
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