Zero damage Ultra-Low-K etch using the precursor CONDensation technique

Información del proyecto

ULKCOND

Identificador del acuerdo de subvención: 708106

DOI

10.3030/708106

Proyecto cerrado

Fecha de la firma de la CE 11 Marzo 2016

Fecha de inicio 1 Abril 2016

Fecha de finalización 31 Marzo 2018

Financiado con arreglo a

• EXCELLENT SCIENCE - Marie Skłodowska-Curie Actions

Coste total

€ 160 800,00

Aportación de la UE

€ 160 800,00

Coordinado por

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM
Belgium

Objetivo

Since the beginning of the electronic evolution, size of transistor never stops to decrease accordingly to Moore’s law. This scaling applies also to the interconnects, composed by conductor and insulating materials, leading to an overall increase of the resistivity of the conductor and the dielectric’s capacitance, ultimately causing delayed signal transmission (so-called RC delay). In order to decrease the resistivity, Al was replaced by Cu as a conductor. The circuit’s capacitance can be lowered by using materials with lower dielectric permittivity, named low-k’s. Nowadays, the most successful low-k dielectrics are porous organo-silicate glasses, with porosity up to 50%, pore size around 1.5-2 nm and k-values down to 1.8 (k=4.2 for bulk SiO2). Interconnects are nowadays built by the Damascene technique, where the dielectric is first deposited, then locally etched away, followed by metal deposition in the patterned structure and polishing for metal excess removal. Due to their intrinsic porosity, most of processing steps cause low-k damage, amongst which plasma etching is the most damaging. The present proposal aims at understanding and optimizing zero-damage cryogenic etching of low-k materials, compatible with the micro-electronics industry (at temperature above -60°C). Besides the improvement of the etching process and the better understanding of reactions damaging the low-k materials during plasma etching, this work will investigate the phenomenon of micro-capillary condensation into porous materials, which is not widely explored and can lead to other applications in micro-electronics and in other nanotechnology domains. This research project will contribute to enable the so-called 5nm node in future CMOS manufacturing, and as a consequence it will have a wide economic impact. Finally, this research will allow the applicant to extend his technical and project management skills, strengthening his profile for a future career in the semiconductor industry or R&D.

Ámbito científico (EuroSciVoc)

• ingeniería y tecnología › nanotecnología
• ciencias naturales › ciencias físicas › física de plasmas
• ingeniería y tecnología › ingeniería de materiales
• ingeniería y tecnología › ingeniería eléctrica, ingeniería electrónica, ingeniería de la información › ingeniería electrónica › sensores
• ciencias naturales › ciencias físicas › electromagnetismo y electrónica › microelectrónica

Programa(s)

• H2020-EU.1.3. - EXCELLENT SCIENCE - Marie Skłodowska-Curie Actions PROGRAMA PRINCIPAL
  
• H2020-EU.1.3.2. - Nurturing excellence by means of cross-border and cross-sector mobility
  

Tema(s)

• MSCA-IF-2015-EF - Marie Skłodowska-Curie Individual Fellowships (IF-EF)
  

Régimen de financiación

MSCA-IF-EF-ST - Standard EF

Convocatoria de propuestas

H2020-MSCA-IF-2015

Coordinador

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM

• Aportación neta de la UEn: € 160 800,00
• Dirección: KAPELDREEF 75 ; 3001 Leuven ; Bélgica
• Región: Vlaams Gewest › Prov. Vlaams-Brabant › Arr. Leuven
• Tipo de actividad: Research Organisations
• Coste total: € 160 800,00