Magnetic non-volatile Random Access Memory for SPACE with Serial interface

Projektinformationen

MNEMOSYNE

ID Finanzhilfevereinbarung: 870415

DOI

10.3030/870415

Projekt abgeschlossen

EK-Unterschriftsdatum 18 Dezember 2019

Startdatum 1 Januar 2020

Enddatum 31 Januar 2024

Finanziert unter

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies – Space

Gesamtkosten

€ 3 038 989,38

EU-Beitrag

€ 3 038 380,00

Koordiniert durch

3D PLUS SA
France

Periodic Reporting for period 2 - MNEMOSYNE (Magnetic non-volatile Random Access Memory for SPACE with Serial interface)

Berichtszeitraum: 2021-07-01 bis 2024-01-31

Zusammenfassung vom Kontext und den Gesamtzielen des Projekts

MNEMOSYNE project coordinated by 3D PLUS aim to develop the first EU independent radiation hardened high density non-volatile memory (NVM) ASIC, using Magnetic RAM (MRAM) technology and the expertise of 6 key partners specialized in design, radiation hardening and performant components for space and aerospace applications.
Non-dependent access to space is a crucial prerequisite for upholding Europe's sovereign right to determine its economic and political future. Achieving this sovereignty requires strong and reliable technological control. Despite Europe's impressive space industry, it still needs to source some high-performance components from outside the continent, often facing restrictive conditions. Thus, achieving non-dependence is a pivotal goal of the European Space Strategy, as the EU satellite industry contends with fierce competition from the US, Russia, and China.
In the fiercely competitive space industry, memory components are critical. For space applications, program memory demands the highest reliability, zero error tolerance, and exceptional radiation hardness, as it directly affects system power-up. As system performance requirements escalate, integrated circuits (ICs) become increasingly dense. Modern space program memory must offer higher speed and density. For instance, the European rad-hard FPGA BRAVE NG-Medium, currently under development, requires at least 13 Mb for its configuration. Future generations, NG-Large and NG-Ultra, will need 128 Mb and up to 512 Mb of high-speed, low pin-count configuration chip. Currently, Europe lacks a radiation-hardened memory component for this critical need.
After over three years of work on the Mnemosyne project, significant advancements beyond the current state of the art have been achieved. A new generation of radiation-hardened high-density NVM ASIC, featuring both serial and parallel interfaces, has been developed using the most matured and commercially available European technology; the 22 nm FDSOI Magnetic RAM (MRAM).

Arbeit, die ab Beginn des Projekts bis zum Ende des durch den Bericht erfassten Berichtszeitraums geleistet wurde, und die wichtigsten bis dahin erzielten Ergebnisse

A total of seven work packages were completed as part of the Mnemosyne project. From gathering end-user requirements to creating design specifications, Mnemosyne designed, registered, packaged, tested and evaluated two ASICs: Mnemosyne test vehicle and Mnemosyne prototype. Digital and analog IP development, radiation hardening through circuit and layout design, and the creation of a test vehicle and prototype were all implemented. This comprehensive approach covered all aspects of ASIC design, including analog circuit design, digital code design, library development, place-and-route (P&R) flow, and verification plus testing. For radiation hardening by design (RHBD), the analog IP and MRAM peripheral blocks were created using an analog flow, with SET simulations verifying single event behavior. The digital P&R flow included extra checks to ensure correct rad-hard performance. A 2D breadboard based on an FPGA was designed and manufactured to ensure the ASIC digital IP design was "first time right."
The RHBD works performed and achieved including:
-The STT MRAM cells are validated in term of SEU immunity for space application;
-The RHBD SEE performances are validated for group of IPs
-Specific RHBD technique has been applied to mitigate observed SET and SEL;
-After SEL observation and correction, RHBD FDSOI SEL immune design are validated;
-The RHBD TID performances are validated for group of IPs;
Several radiation characterization test benches were developed and manufactured to assess TID, SEE, and laser aspects, evaluating the technology and design to pinpoint radiation-sensitive areas. Reliability and functionality tests assessed the test vehicle and prototype for compatibility with other space components and performance in harsh space environments. The prototype was validated on test benches to assess the ASIC's reliability and functionality, thus verifying the design specifications.
During Mnemosyne project, a rad-hard NVM block (128 Mbit density) and a set of rad-had analog IPs were delivered and validated under space radiation conditions. This NVM ASIC is used to achieve up to 1 Gbit density of program memory chip using 3D PLUS stacking process.

Fortschritte, die über den aktuellen Stand der Technik hinausgehen und voraussichtliche potenzielle Auswirkungen (einschließlich der bis dato erzielten sozioökonomischen Auswirkungen und weiter gefassten gesellschaftlichen Auswirkungen des Projekts)

The Mnemosyne prototype is a game-changer for high-speed, high-reliability, high-density, and radiation-tolerant space applications. It replaces OTP PROM, EEPROM, and first-generation Toggle MRAM, increasing capacity by a factor of 8 to 1000. Compared to existing NOR FLASH, it maintains the same capacity while enhancing radiation tolerance from 20 Krad to 100 Krad. Additionally, it offers SEL/SEU/SEFI immunity up to 60 MeV.cm²/mg, unmatched by NOR FLASH. The Mnemosyne prototype offers unique density and reliability advantages over CBRAM, PCRAM, and ReRAM. Designed for both MCU/FPGA program memories chips, it is ideal for configuring large SRAM-based FPGAs, supporting high-performance systems and "New Space" projects in the European space industry. This is the perfect companion of the next generation of FPGA supported by Europe.
Additionally, Mnemosyne provides 128 Mb standalone space NVM and outputs space NVM IPs or macros for next-generation high-performance ASIC designs. This enhancement will significantly boost the performance of European high-performance or high-reliability ASICs, allowing European satellites to compete effectively with non-European suppliers without export/import issues.
The MNEMOSYNE project strengthens the EU's position in the space industry and significantly impacts the field of Electrical, Electronic, and Electromechanical (EEE) components, which has been dominated by players outside Europe. By enhancing Europe's non-dependence on space access, the Mnemosyne prototype becomes a crucial component for many space systems. This aligns with the Harmonised European Space Technology Roadmaps, particularly in microelectronics: ASIC & FPGA.
The key innovations of the project are listed below:
-The first European RHBD (radiation hardened by design) space NVM with density higher than 1Mb;
-The first European embedded RHBD high performance space NVM IP core on process lower than 28nm;
-The first new generation Spin-Transfer Torque (STT) MRAM for space application;
-The first RHBD applied on 22nm FDSOI on both digital and analog IPs’ for TID & SEE mitigations;
-A space product family prototypes from 128Mb to 1Gb with not only required serial interface and also additional parallel interface are available.
Achieving TRL5 by the end of the project, full production of the chip is expected soon. This development is in line with the EU effort to reduce EEE components imports from 85% to 50%.
Furthermore, radiation-hardened MRAM and embedded NVM IP cores positively impact aviation, ground, and accelerator applications. Thus, increasing the global competitiveness of European industry vendors, offering reliable and safe systems in markets where failure is not an option

picture taken during the kick off meeting