Cryogenic 3D Nanoelectronics

Informations projet

SEQUENCE

N° de convention de subvention: 871764

DOI

10.3030/871764

Projet clôturé

Date de signature de la CE 5 Decembre 2019

Date de début 1 Janvier 2020

Date de fin 31 Juillet 2023

Financé au titre de

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Coût total

€ 4 466 278,75

Contribution de l’UE

€ 4 466 277,00

Coordonné par

LUNDS UNIVERSITET
Sweden

CORDIS fournit des liens vers les livrables publics et les publications des projets HORIZON.

Les liens vers les livrables et les publications des projets du 7e PC, ainsi que les liens vers certains types de résultats spécifiques tels que les jeux de données et les logiciels, sont récupérés dynamiquement sur OpenAIRE .

Livrables

Documents, reports (16)

Final benchmarking towards evolving wideband communication and sensing including identification of limiting factors
Initial benchmarking towards evolving wideband communication and sensing
Final report on electrical parameter, interface dielectric trap and RF (S parameter and NF) characterization of devices operated at cryogenic condition

Final report on electrical parameter interface dielectric trap and RF S parameter and NF characterization of devices operated at cryogenic condition

Report on first version of device compact models for LF and RF circuit simulation
First report on interface dielectric trap and RF (S parameter and NF) characterization of devices operated at cryogenic condition
Web site launch
Report on extremely low temperature (20mK-4K) device characterization

Report on extremely low temperature 20mK4K device characterization

Road map for integrated and improved quantum computer electronics
Report on device compact modelling for LF and RF circuit simulation
Report on self heating device characterization by thermal and electrical techniques
Review of key building blocks for cryogenic logic and space, 40-70 K, as well as wideband communication, RT
First report on electrical characterization and parameter extraction of devices operated at cryogenic condition
External Communication Plan
Dissemination Plan
Final Dissemination Plan
Initial report on circuit design with layouts and simulated performance

Publications

Peer reviewed articles (17)

On the diffusion current in a MOSFET operated down to deep cryogenic temperatures

Auteurs: G. Ghibaudo, M. Aouad, M. Casse, T. Poiroux, C. Theodorou
Publié dans: Solid-State Electronics, Numéro 176, 2021, Page(s) 107949, ISSN 0038-1101
Éditeur: Pergamon Press Ltd.
DOI: 10.1016/j.sse.2020.107949

Performance and Low-Frequency Noise of 22-nm FDSOI Down to 4.2 K for Cryogenic Applications

Auteurs: Bruna Cardoso Paz, Mikael Casse, Christoforos Theodorou, Gerard Ghibaudo, Thorsten Kammler, Luca Pirro, Maud Vinet, Silvano de Franceschi, Tristan Meunier, Fred Gaillard
Publié dans: IEEE Transactions on Electron Devices, Numéro 67/11, 2020, Page(s) 4563-4567, ISSN 0018-9383
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ted.2020.3021999

First Demonstration of Distributed Amplifier MMICs With More Than 300-GHz Bandwidth

Auteurs: Fabian Thome, Arnulf Leuther
Publié dans: IEEE Journal of Solid-State Circuits, 2021, Page(s) 1-1, ISSN 0018-9200
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/jssc.2021.3052952

Optimization of Near‐Surface Quantum Well Processing

Auteurs: Patrik Olausson, Lasse Södergren, Mattias Borg, Erik Lind
Publié dans: physica status solidi (a), Numéro 218/7, 2021, Page(s) 2000720, ISSN 1862-6300
Éditeur: Wiley - V C H Verlag GmbbH & Co.
DOI: 10.1002/pssa.202000720

Tuning of Source Material for InAs/InGaAsSb/GaSb Application-Specific Vertical Nanowire Tunnel FETs

Auteurs: Abinaya Krishnaraja, Johannes Svensson, Elvedin Memisevic, Zhongyunshen Zhu, Axel R. Persson, Erik Lind, Lars Reine Wallenberg, Lars-Erik Wernersson
Publié dans: ACS Applied Electronic Materials, Numéro 2/9, 2020, Page(s) 2882-2887, ISSN 2637-6113
Éditeur: ACS
DOI: 10.1021/acsaelm.0c00521

Evidence of 2D intersubband scattering in thin film fully depleted silicon-on-insulator transistors operating at 4.2 K

Auteurs: Mikaël Cassé, Bruna Cardoso Paz, Gérard Ghibaudo, Thierry Poiroux, Emmanuel Vincent, Philippe Galy, André Juge, Fred Gaillard, Silvano de Franceschi, Tristan Meunier, Maud Vinet
Publié dans: Applied Physics Letters, Numéro 116/24, 2020, Page(s) 243502, ISSN 0003-6951
Éditeur: American Institute of Physics
DOI: 10.1063/5.0007100

Simulation of low-noise amplifier with quantized ballistic nanowire channel

Auteurs: Christian Marty, Clarissa Convertino, Cezar Zota
Publié dans: Semiconductor Science and Technology, Numéro 35/11, 2020, Page(s) 115027, ISSN 0268-1242
Éditeur: Institute of Physics Publishing
DOI: 10.1088/1361-6641/abb841

The Role of Oxide Traps Aligned With the Semiconductor Energy Gap in MOS Systems

Auteurs: Enrico Caruso, Jun Lin, Scott Monaghan, Karim Cherkaoui, Farzan Gity, Pierpaolo Palestri, David Esseni, Luca Selmi, Paul K. Hurley
Publié dans: IEEE Transactions on Electron Devices, Numéro 67/10, 2020, Page(s) 4372-4378, ISSN 0018-9383
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ted.2020.3018095

A hybrid III–V tunnel FET and MOSFET technology platform integrated on silicon

Auteurs: Clarissa Convertino, Cezar B. Zota, Heinz Schmid, Daniele Caimi, Lukas Czornomaz, Adrian M. Ionescu, Kirsten E. Moselund
Publié dans: Nature Electronics, Numéro 4/2, 2021, Page(s) 162-170, ISSN 2520-1131
Éditeur: Nature
DOI: 10.1038/s41928-020-00531-3

InGaAs MOSHEMT W -Band LNAs on Silicon and Gallium Arsenide Substrates

Auteurs: Fabian Thome, Felix Heinz, Arnulf Leuther
Publié dans: IEEE Microwave and Wireless Components Letters, Numéro 30/11, 2020, Page(s) 1089-1092, ISSN 1531-1309
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/lmwc.2020.3025674

III-V-on-Si transistor technologies: Performance boosters and integration

Auteurs: D. Caimi, H. Schmid, T. Morf, P. Mueller, M. Sousa, K.E. Moselund, C.B. Zota
Publié dans: Solid-State Electronics, Numéro 185, 2021, Page(s) 108077, ISSN 0038-1101
Éditeur: Pergamon Press Ltd.
DOI: 10.1016/j.sse.2021.108077

Scaled III-V-on-Si Transistors for Low-Power Logic and Memory Applications

Auteurs: Daniele Caimi, Marilyne Sousa, Siegfried Karg and Cezar B. Zota
Publié dans: Japanese Journal of Applied Physics, Numéro 60/SB, 2021, Page(s) SB0801, ISSN 0021-4922
Éditeur: IOP Science
DOI: 10.35848/1347-4065/abd707

Generalized Boltzmann relations in semiconductors including band tails

Auteurs: Arnout Beckers, Dominique Beckers, Farzan Jazaeri, Bertrand Parvais, Christian Enz
Publié dans: Journal of Applied Physics, Numéro 129/4, 2021, Page(s) 045701, ISSN 0021-8979
Éditeur: American Institute of Physics
DOI: 10.1063/5.0037432

Mobility of near surface MOVPE grown InGaAs/InP quantum wells

Auteurs: Lasse Södergren, Navya Sri Garigapati, Mattias Borg, Erik Lind
Publié dans: Applied Physics Letters, Numéro 117/1, 2020, Page(s) 013102, ISSN 0003-6951
Éditeur: American Institute of Physics
DOI: 10.1063/5.0006530

Heterogeneous Integration of III-V Materials by Direct Wafer Bonding for High-Performance Electronics and Optoelectronics

Auteurs: Daniele Caimi, Preksha Tiwari, Marilyne Sousa, Kirsten E. Moselund, Cezar B. Zota
Publié dans: IEEE Transactions on Electron Devices, 2021, Page(s) 1-8, ISSN 0018-9383
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ted.2021.3067273

Millimeter-Wave Vertical III-V Nanowire MOSFET Device-to-Circuit Co-Design

Auteurs: Stefan Andric, Lars Ohlsson Fhager, Lars-Erik Wernersson
Publié dans: IEEE Transactions on Nanotechnology, Numéro 20, 2021, Page(s) 434-440, ISSN 1536-125X
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tnano.2021.3080621

Cryogenic Operation of Thin-Film FDSOI nMOS Transistors: The Effect of Back Bias on Drain Current and Transconductance

Auteurs: M. Casse, B. Cardoso Paz, G. Ghibaudo, T. Poiroux, S. Barraud, M. Vinet, S. de Franceschi, T. Meunier, F. Gaillard
Publié dans: IEEE Transactions on Electron Devices, Numéro 67/11, 2020, Page(s) 4636-4640, ISSN 0018-9383
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ted.2020.3022607

Conference proceedings (6)

Design of III-V Vertical Nanowire MOSFETs for Near-Unilateral Millimeter-Wave Operation

Auteurs: Stefan Andrić, Lars Ohlsson-Fhager, Lars-Erik Wernersson
Publié dans: Numéro 10-15 Jan. 2021, 2020
Éditeur: IEEE

Poisson-Schrödinger simulation of inversion charge in FDSOI MOSFET down to 0K - Towards compact modeling for cryo CMOS application

Auteurs: M. Aouad, S. Martinie, F. Triozon, T. Poiroux, M. Vinet, G. Ghibaudo
Publié dans: 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2020, Page(s) 1-4, ISBN 978-1-7281-8765-5
Éditeur: IEEE
DOI: 10.1109/eurosoi-ulis49407.2020.9365297

Vertical InAs/InGaAsSb/GaSb Nanowire Tunnel FETs on Si with Drain Field-Plate and EOT = 1 nm Achieving S min = 32 mV/dec and g m /I D = 100 V -1

Auteurs: Abinaya Krishnaraja, Johannes Svensson, Lars-Erik Wernersson
Publié dans: 2020 IEEE Silicon Nanoelectronics Workshop (SNW), 2020, Page(s) 17-18, ISBN 978-1-7281-9735-7
Éditeur: IEEE
DOI: 10.1109/snw50361.2020.9131656

III-V Nanowire MOSFETs: RF-Properties and Applications

Auteurs: Lars-Erik Wernersson
Publié dans: 2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2020, Page(s) 1-4, ISBN 978-1-7281-9749-4
Éditeur: IEEE
DOI: 10.1109/bcicts48439.2020.9392932

Cryo-CMOS Compact Modeling

Auteurs: Christian Enz, Arnout Beckers, Farzan Jazaeri
Publié dans: 2020 IEEE International Electron Devices Meeting (IEDM), 2020, Page(s) 25.3.1-25.3.4, ISBN 978-1-7281-8888-1
Éditeur: IEEE
DOI: 10.1109/iedm13553.2020.9371894

Ultra-Low Power Scaled III-V-on-Si 1T-DRAMs With Quantum Well Heterostructures

Auteurs: C. Convertino, L. Vergano, L. Czornomaz, C. B. Zota, S. Karg
Publié dans: 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2020, Page(s) 1-4, ISBN 978-1-7281-8765-5
Éditeur: IEEE
DOI: 10.1109/eurosoi-ulis49407.2020.9365288

Book chapters (1)

Low Temperature Characterization and Modeling of FDSOI Transistors for Cryo CMOS Applications

Auteurs: Mikaël Cassé, Gérard Ghibaudo
Publié dans: Low-Temperature Technologies [Working Title], 2021
Éditeur: IntechOpen
DOI: 10.5772/intechopen.98403