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Modeling Unconventional Nanoscaled Device FABrication

Periodic Reporting for period 2 - MUNDFAB (Modeling Unconventional Nanoscaled Device FABrication)

Periodo di rendicontazione: 2021-07-01 al 2023-06-30

The progressing development of big data and mobility applications as well as of the Internet of Things requires the further miniaturization of electronic circuits. Sophisticated manufacturing techniques for computer chips, such as the sequential 3D integration of devices, are a key to success. In addition to experimental investigations, the use of Technology-Computer Aided Design (TCAD) programs is of particular importance: Simulations allow significant cost and time savings in the development of new technologies and devices in industrial environments. The improvement of simulation tools is therefore the key focus of our EU project MUNDFAB („Modeling Unconventional Nanoscaled Device FABrication“).

Simulation programs based on classical continuum approaches are of limited use for nanometer-sized structures such as investigated in MUNDFAB. This is because they are not able to accurately predict relevant effects, for instance the reduced electrical activation of dopants, special cases of topography modifications, or the formation and growth of defects. In particular, existing models do not allow the precise simulation of low-temperature processes, which are essential for the sequential 3D integration of devices.

This is where the MUNDFAB project comes in: In order to optimize modeling for an accurate prediction of the processing of, e.g. silicon or silicon-germanium layers used for nano-sized devices, dedicated experiments were carried out to improve the simulation models. For the simulations, the researchers used commercial software tools, open-source applications as well as simulation programs provided by the project partners, which were adapted and further developed in the project. Simulators that can directly represent the atomistic structure of the systems under consideration allow a particularly realistic modeling of the nanostructures. The final result is the establishment of a calibrated simulation toolchain, which allows the computer-based virtualization of the manufacturing and sequential 3D integration of nano-sized devices.
The main emphasis of the work in MUNDFAB was on a completion of the experimental knowledge for process steps performed at very low thermal budgets on silicon and high-mobility silicon-germanium layers, as well as on a development of predictive process models for such systems. Whenever the models could not be implemented in state-of-the-art commercial TCAD programs, the open-source Kinetic Monte Carlo super-Lattice code MulSKIPS (https://github.com/MulSKIPS/MulSKIPS(si apre in una nuova finestra)) was used.

For ion implantation processes, the simulation goals were to improve models for implant temperatures from room temperature to 500°C. The simulations used a hybrid approach, combining Kinetic Monte Carlo (KMC) and continuum methods to reproduce damage formation, diffusion and activation.

The formation of nickel silicide even exceeds the capabilities of atomistic Lattice Kinetic Monte Carlo (LKMC) approaches. We developed an in-cell Monte Carlo simulation tool for silicidation studies which can simulate various silicide compounds, such as Pt-Si and Ni-Si, and accommodates changes in phase variables and local composition.

To simulate epitaxial growth of Si and SiGe hetero-structures by chemical vapour deposition (CVD), two different LKMC models considering the molecular arrival rates of the gas flows, surface chemistry for adsorption, decomposition, and desorption, as well as atomic lattice bonding have been used: Firstly, the LKMC model implemented in Sentaurus Process of Synopsys was used for the prediction of growth rates, Ge mole fraction and doping. Secondly, a new LKMC model implemented in MulSKIPS was developed to include the formation of defects during epitaxy using a super-Lattice Kinetic Monte Carlo (KMCsL) scheme.

Ab initio simulations based on Density Functional Theory (DFT) calculations have been carried out to compute the energies involved in the reactions of SiH4 and HCl with a silicon surface. In parallel, dedicated experiments have been carried out to study the electrical activation of in situ doped SiGe:B layers and the influence of nanosecond laser anneals (LA) in the sub-melt regime.

Computational methodologies for the simulation of LA were based on a hybrid atomistic-continuum methodology, combining the use of atomic resolution for particle kinetics (including phase changes from solid to liquid and vice versa, based on a KMCsL solver) with a continuum representation of the thermal and electromagnetic fields generated during laser irradiation. Within this methodological scheme, atomistic aspects that were previously “invisible” to LA simulation techniques, like the generation or annihilation of point and extended defects, or the presence of surface roughness and facet-dependent regrowth mechanisms, are now naturally incorporated within the LA modelling procedure.

Understanding the reliability of a device requires knowledge about its microscopic structure. For this purpose, we utilized predictions based on DFT in conjunction with Comphy (https://comphy.eu/(si apre in una nuova finestra)) a compact device simulator, to identify defects in fully processed devices, which are responsible for device degradation. With this methodology we demonstrated that hydrogen-related defects are mostly responsible for device degradation.

We further utilized a multi-scale approach, in which a machine-learning force-field is trained on data from DFT or other electronic structure methods like DFTB. Such a potential can then be used to study the system dynamics with ab-initio accuracy on much bigger systems. This approach allowed us for the first time to simulate all atomistic details of the whole silicon oxidation process.

To assess the models developed in the end, suitable test devices were defined at the beginning of the project. Based on the advanced fabrication processes of these demonstrators, complete simulation toolchains were developed combining continuum simulations in commercial TCAD tools and the atomistic models developed within MUNDFAB. Finally, STMicroelectronics validated the toolchains as well as the models and methodologies developed in MUNDFAB based on the defined test devices.

The work in MUNDFAB resulted in 7 invited and 63 contributed presentations at workshops and conferences as well as in 39 publications in refereed journals and conference proceedings. To enable intensive discussions within the community, a symposium on “Materials engineering for advanced semiconductor devices” was organized at the Spring Meeting 2023 of the European Materials Research Society (E-MRS).
The work in MUNDFAB provides Technology-Computer-Aided Design (TCAD) with the features necessary for the design and optimization of new generations of electron devices in industry like: Predictivity for low-temperature processing below 600 °C as needed for 3D sequential integration; processing of nanoscaled devices based on high-mobility SiGe materials; simulation of topography changes on the nanoscale; and a methodology to link defect formation with the reliability of electron devices. With TCAD being an indispensable tool particularly in the early stages of the development, MUNDFAB will thus contribute considerably to the European industry’s capability to design the next device generations.
Well-calibrated MulSKIPS simulation of Si CVD-grown source and drain of an FDSOI device
Calibration of the MulSKIPS laser annealing module for SiGe
Simulated defect distribution after ion implantation at elevated temperatures
KMCsL simulation of CVD growth of a Si fin using MulSKIPS
Molecular dynamics simulation of large system based on a machine-learning model
Coupled FEM-LKMC atomistic laser annealing simulations of SiGe 3D systems
KMCsL simulation of CVD growth of 30 nm Si(1-x)Ge(x):B layer on a Si(001)
Stages of the oxidation of silicon on a microscopic level
Silicidation reaction of a nanocrystalline nickel film with a silicon substrate
Vertical nanowire array transistor used as one of the test devices for the models developed
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