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Integration of III-V Nanowire Semiconductors for next Generation High Performance CMOS SOC Technologies

Deliverables

Improved noise measurements and RF noise model. p-type noise

Improved noise measurements and RF noise model. p-type noise

PA and LNA data sheet

PA and LNA data sheet

Web site launch and Press Release for the INSIGHT project

Web site launch and Press Release for the INSIGHT project

Correlation between CV, 1/f, Hysteresis gm(w) on the border trap density

Correlation between CV, 1/f, Hysteresis gm(w) on the border trap density.

Final report on RF-transistors

Final report on RF-transistors

Data from first small signal model obtained from existing nanowire technology

Data from first small signal model obtained from existing nanowire technology

First noise measurements and RF noise model

First noise measurements and RF noise model

Second update on Dissemination Plan

Second update on dissemination plan. It will be included in the “plan for Dissemination and Exploitation”.

Circuit-level Benchmarking Report

Circuit-level Benchmarking Report

External Communication Plan

External Communication Plan

Report on high voltage (3-6V) gate stack development

Report on high voltage (3-6V) gate stack development

Searching for OpenAIRE data...

Publications

First RF characterization of InGaAs replacement metal gate (RMG) nFETs on SiGe-OI FinFETs fabricated by 3D monolithic integration

Author(s): V. Deshpande, V. Djara, E. O'Connor, D. Caimi, M. Sousa, L. Czornomaz, J. Fompeyrine, P. Hashemi, K. Balakrishnan
Published in: 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Issue Yearly, 2016, Page(s) 127-130
DOI: 10.1109/ULIS.2016.7440069

Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

Author(s): Martin Berg, Karl-Magnus Persson, Olli-Pekka Kilpi, Johannes Svensson, Erik Lind, Lars-Erik Wernersson
Published in: 2015 IEEE International Electron Devices Meeting (IEDM), 2015, Page(s) 31.2.1-31.2.4
DOI: 10.1109/IEDM.2015.7409806

Single suspended InGaAs nanowire MOSFETs

Author(s): Cezar B. Zota, Lars-Erik Wernersson, Erik Lind
Published in: 2015 IEEE International Electron Devices Meeting (IEDM), 2015, Page(s) 31.4.1-31.4.4
DOI: 10.1109/IEDM.2015.7409808

Initial investigation on the impact of in situ hydrogen plasma exposure to the interface between molecular beam epitaxially grown p-Ga0.7In0.3Sb (100) and thermal atomic layer deposited (ALD) Al2O3

Author(s): Millar, D., Peralagu, U., Fu, Y.-C., Li, X., Steer, M., and Thayne, I.
Published in: WoDIM, Issue Yearly; Session 4: III-V FETs, 2016, Page(s) N/A

Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si

Author(s): Adam Jonsson, Johannes Svensson, Lars-Erik Wemersson
Published in: 2018 IEEE International Electron Devices Meeting (IEDM), 2018, Page(s) 39.3.1-39.3.4
DOI: 10.1109/iedm.2018.8614685

Sub-100-nm gate-length scaling of vertical InAs/InGaAs nanowire MOSFETs on Si

Author(s): Olli-Pekka Kilpi, Johannes Svensson, Lars-Erik Wernersson
Published in: 2017 IEEE International Electron Devices Meeting (IEDM), 2017, Page(s) 17.3.1-17.3.4
DOI: 10.1109/iedm.2017.8268408

Profiling border-traps by TCAD analysis of multifrequency CV-curves in Al<inf>2</inf>O<inf>3</inf>/InGaAs stacks

Author(s): E. Caruso, J. Lin, K. F. Burke, K. Cherkaoui, D. Esseni, F. Gity, S. Monaghan, P. Palestri, P. Hurley, L. Selmi
Published in: 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2018, Page(s) 1-4
DOI: 10.1109/ulis.2018.8354757

Low-Temperature Front-Side BEOL Technology with Circuit Level Multiline Thru-Reflect-Line Kit for III-V MOSFETs on Silicon

Author(s): Stefan Andric, Lars Ohlsson, Lars-Erik Wenrersson
Published in: 2019 92nd ARFTG Microwave Measurement Conference (ARFTG), 2019, Page(s) 1-4
DOI: 10.1109/arftg.2019.8637222

First demonstration of 3D SRAM through 3D monolithic integration of InGaAs n-FinFETs on FDSOI Si CMOS with inter-layer contacts

Author(s): V. Deshpande, H. Hahn, E. O'Connor, Y. Baumgartner, M. Sousa, D. Caimi, H. Boutry, J. Widiez, L. Brevard, C. Le Royer, M. Vinet, J. Fompeyrine, L. Czornomaz
Published in: 2017 Symposium on VLSI Technology, 2017, Page(s) T74-T75
DOI: 10.23919/vlsit.2017.7998205

Integration of III–V nanowires for the next RF- and logic technology generation

Author(s): Lars-Erik Wernersson
Published in: 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2017, Page(s) 1-2
DOI: 10.1109/vlsi-tsa.2017.7942489

A scaled replacement metal gate InGaAs-on-Insulator n-FinFET on Si with record performance

Author(s): H. Hahn, V. Deshpande, E. Caruso, S. Sant, E. O'Connor, Y. Baumgartner, M. Sousa, D. Caimi, A. Olziersky, P. Palestri, L. Selmi, A. Schenk, L. Czornomaz
Published in: 2017 IEEE International Electron Devices Meeting (IEDM), 2017, Page(s) 17.5.1-17.5.4
DOI: 10.1109/iedm.2017.8268410

Hybrid InGaAs/SiGe CMOS circuits with 2D and 3D monolithic integration

Author(s): V. Deshpande, H. Hahn, V. Djara, E. O'Connor, D. Caimi, M. Sousa, J. Fompeyrine, L. Czornomaz
Published in: 2017 47th European Solid-State Device Research Conference (ESSDERC), 2017, Page(s) 244-247
DOI: 10.1109/essderc.2017.8066637

InGaAs FinFETs 3D Sequentially Integrated on FDSOI Si CMOS with Record Perfomance

Author(s): C. Convertino, C. B. Zota, D. Caimi, M. Sousa, L. Czornomaz
Published in: 2018 48th European Solid-State Device Research Conference (ESSDERC), 2018, Page(s) 162-165
DOI: 10.1109/essderc.2018.8486862

First InGaAs lateral nanowire MOSFET RF noise measurements and model

Author(s): Lars Ohlsson, Fredrik Lindelow, Cezar B. Zota, Matthias Ohlrogge, Thomas Merkle, Lars-Erik Wernersson, Erik Lind
Published in: 2017 75th Annual Device Research Conference (DRC), 2017, Page(s) 1-2
DOI: 10.1109/drc.2017.7999451

High Performance Quantum Well InGaAs-On-Si MOSFETs With sub-20 nm Gate Length For RF Applications

Author(s): C. B. Zota, C. Convertino, Y. Baumgartner, M. Sousa, D. Caimi, L. Czornomaz
Published in: 2018 IEEE International Electron Devices Meeting (IEDM), 2018, Page(s) 39.4.1-39.4.4
DOI: 10.1109/iedm.2018.8614530

InGaAs-on-Insulator FinFETs with Reduced Off-Current and Record Performance

Author(s): C. Convertino, C. Zota, S. Sant, F. Eltes, M. Sousa, D. Caimi, A. Schenk, L. Czornomaz
Published in: 2018 IEEE International Electron Devices Meeting (IEDM), 2018, Page(s) 39.2.1-39.2.4
DOI: 10.1109/iedm.2018.8614640

Investigation of InAs/GaSb tunnel diodes on SOI

Author(s): C. Convertino, D. Cutaia, H. Schmid, N. Bologna, P. Paletti, A.M. Ionescu, H. Riel, K. E. Moselund
Published in: 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017, Page(s) 148-151
DOI: 10.1109/ulis.2017.7962586

Properties of III–V nanowires: MOSFETs and TunnelFETs

Author(s): Lars-Erik Wernersson
Published in: 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017, Page(s) 99-100
DOI: 10.1109/ulis.2017.7962611

A 250 GHz millimeter wave amplifier MMIC based on 30 nm metamorphic InGaAs MOSFET technology

Author(s): Arnulf Leuther, Matthias Ohlrogge, Lukas Czornomaz, Thomas Merkle, Frank Bernhardt, Axel Tessmann
Published in: 2017 12th European Microwave Integrated Circuits Conference (EuMIC), 2017, Page(s) 130-133
DOI: 10.23919/eumic.2017.8230677

Monolithic integration of multiple III-V semiconductors on Si

Author(s): H. Schmid, B. Mayer, J. Gooth, S. Wirths, L. Czornomaz, H. Riel, S. Mauthe, C. Convertino, K. E. Moselund
Published in: 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017, Page(s) 1-3
DOI: 10.1109/s3s.2017.8309200

InGaAs-on-Si (Ge) 3D Monolithic Technology for CMOS and More-than-Moore

Author(s): V. Deshpande, V. Djara, T. Morf, P. Hashemi, E. O’Connor, K. Balakrishnan, D. Caimi, M. Sousa, L. Czornomaz and J. Fompeyrine
Published in: Int'l Conf. on Solid State Devices and Materials (SSDM),, Issue Book of Extended Abstracts in 2016, 2016

80 nm InGaAs MOSFET W-band low noise amplifier

Author(s): Amulf Leuther, Matthias Ohlrogge, Lukas Czornomaz, Thomas Merkle, Frank Bernhardt, Axel Tessmann
Published in: 2017 IEEE MTT-S International Microwave Symposium (IMS), 2017, Page(s) 1133-1136
DOI: 10.1109/mwsym.2017.8058798

Vertical heterojunction InAs/InGaAs nanowire MOSFETs on Si with I<inf>on</inf> = 330 μA/μm at I<inf>off</inf> = 100 nA/μm and V<inf>D</inf> = 0.5 V

Author(s): Olli-Pekka Kilpi, Jun Wu, Johannes Svensson, Erik Lind, Lars-Erik Wernersson
Published in: 2017 Symposium on VLSI Technology, 2017, Page(s) T36-T37
DOI: 10.23919/vlsit.2017.7998191

High Gain 220 - 275 GHz Amplifier MMICs Based on Metamorphic 20 nm InGaAs MOSFET Technology

Author(s): A. Tessmann, A. Leuther, F. Heinz, F. Bernhardt, H. Massler
Published in: 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2018, Page(s) 156-159
DOI: 10.1109/bcicts.2018.8550836

InGaAs-on-Insulator MOSFETs Featuring Scaled Logic Devices and Record RF Performance

Author(s): C. B. Zota, C. Convertino, V. Deshpande, T. Merkle, M. Sousa, D. Caimi, L. Czomomaz
Published in: 2018 IEEE Symposium on VLSI Technology, 2018, Page(s) 165-166
DOI: 10.1109/vlsit.2018.8510631

Monolithic integration of multiple III-V semiconductors on Si for MOSFETs and TFETs

Author(s): H. Schmid, D. Cutaia, J. Gooth, S. Wirths, N. Bologna, K. E. Moselund, H. Riel
Published in: 2016 IEEE International Electron Devices Meeting (IEDM), Issue Yearly, 2016, Page(s) 3.6.1-3.6.4
DOI: 10.1109/IEDM.2016.7838340

InGaAs tri-gate MOSFETs with record on-current

Author(s): Cezar B. Zota, Fredrik Lindelow, Lars-Erik Wernersson, Erik Lind
Published in: 2016 IEEE International Electron Devices Meeting (IEDM), 2016, Page(s) 3.2.1-3.2.4
DOI: 10.1109/IEDM.2016.7838336

InGaAs nanowire MOSFETs with I<inf>ON</inf> = 555 µA/µm at I<inf>OFF</inf> = 100 nA/µm and V<inf>DD</inf> = 0.5 V

Author(s): Cezar B. Zota, Fredrik Lindelow, Lars-Erik Wernersson, Erik Lind
Published in: 2016 IEEE Symposium on VLSI Technology, Issue Yearly, 2016, Page(s) 1-2
DOI: 10.1109/VLSIT.2016.7573418

Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si

Author(s): Martin Berg, Olli-Pekka Kilpi, Karl-Magnus Persson, Johannes Svensson, Markus Hellenbrand, Erik Lind, Lars-Erik Wernersson
Published in: IEEE Electron Device Letters, Issue Volume:PP Issue: 99 , 2016, Page(s) 1-1, ISSN 0741-3106
DOI: 10.1109/LED.2016.2581918

High-Performance Lateral Nanowire InGaAs MOSFETs with Improved On-Current

Author(s): Cezar Zota, Lars-Erik Wernersson, Erik Lind
Published in: IEEE Electron Device Letters, 2016, Page(s) 1-1, ISSN 0741-3106
DOI: 10.1109/LED.2016.2602841

High-Frequency InGaAs Tri-gate MOSFETs with fmax of 400 GHz

Author(s): Cezar Zota, Fredrik Lindelöw, Lars-Erik Wernersson, Erik Lind
Published in: Electronics Letters, 2016, ISSN 0013-5194
DOI: 10.1049/el.2016.3108

Electrical properties of metal/Al 2 O 3 /In 0.53 Ga 0.47 As capacitors grown on InP

Author(s): Philippe Ferrandis, Mathilde Billaud, Julien Duvernay, Mickael Martin, Alexandre Arnoult, Helen Grampeix, Mikael Cassé, Hervé Boutry, Thierry Baron, Maud Vinet, Gilles Reimbold
Published in: Journal of Applied Physics, Issue 123/16, 2018, Page(s) 161534, ISSN 0021-8979
DOI: 10.1063/1.5007920

Low-Frequency Noise in III–V Nanowire TFETs and MOSFETs

Author(s): Markus Hellenbrand, Elvedin Memisevic, Martin Berg, Olli-Pekka Kilpi, Johannes Svensson, Lars-Erik Wernersson
Published in: IEEE Electron Device Letters, Issue 38/11, 2017, Page(s) 1520-1523, ISSN 0741-3106
DOI: 10.1109/led.2017.2757538

A Self-Aligned Gate-Last Process Applied to All-III–V CMOS on Si

Author(s): Adam Jonsson, Johannes Svensson, Lars-Erik Wernersson
Published in: IEEE Electron Device Letters, Issue 39/7, 2018, Page(s) 935-938, ISSN 0741-3106
DOI: 10.1109/led.2018.2837676

Low-frequency noise in nanowire and planar III-V MOSFETs

Author(s): Markus Hellenbrand, Olli-Pekka Kilpi, Johannes Svensson, Erik Lind, Lars-Erik Wernersson
Published in: Microelectronic Engineering, 2019, Page(s) 110986, ISSN 0167-9317
DOI: 10.1016/j.mee.2019.110986

Examining the relationship between capacitance-voltage hysteresis and accumulation frequency dispersion in InGaAs metal-oxide-semiconductor structures based on the response to post-metal annealing

Author(s): Jun Lin, Scott Monaghan, Karim Cherkaoui, Ian M. Povey, Brendan Sheehan, Paul K. Hurley
Published in: Microelectronic Engineering, Issue 178, 2017, Page(s) 204-208, ISSN 0167-9317
DOI: 10.1016/j.mee.2017.05.020

InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities

Author(s): Clarissa Convertino, Cezar Zota, Heinz Schmid, Daniele Caimi, Marilyne Sousa, Kirsten Moselund, Lukas Czornomaz
Published in: Materials, Issue 12/1, 2019, Page(s) 87, ISSN 1996-1944
DOI: 10.3390/ma12010087

Facet-selective group-III incorporation in InGaAs template assisted selective epitaxy

Author(s): Mattias Borg, Lynne Gignac, John Bruley, Andreas Malmgren, Saurabh Sant, Clarissa Convertino, Marta D Rossell, Marilyne Sousa, Chris Breslin, Heike Riel, Kirsten E Moselund, Heinz Schmid
Published in: Nanotechnology, Issue 30/8, 2019, Page(s) 084004, ISSN 0957-4484
DOI: 10.1088/1361-6528/aaf547

High frequency III–V nanowire MOSFETs

Author(s): Erik Lind
Published in: Semiconductor Science and Technology, Issue 31/9, 2016, Page(s) 093005, ISSN 0268-1242
DOI: 10.1088/0268-1242/31/9/093005

Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs

Author(s): Olli-Pekka Kilpi, Johannes Svensson, Erik Lind, Lars-Erik Wernersson
Published in: IEEE Journal of the Electron Devices Society, Issue 7, 2019, Page(s) 70-75, ISSN 2168-6734
DOI: 10.1109/jeds.2018.2878659

20-nm In0.8Ga0.2As MOSHEMT MMIC Technology on Silicon

Author(s): Axel Tessmann, Arnulf Leuther, Felix Heinz, Frank Bernhardt, Laurenz John, Hermann Massler, Lukas Czornomaz, Thomas Merkle
Published in: IEEE Journal of Solid-State Circuits, 2019, Page(s) 1-8, ISSN 0018-9200
DOI: 10.1109/jssc.2019.2915161

Vertical InAs/InGaAs Heterostructure Metal–Oxide–Semiconductor Field-Effect Transistors on Si

Author(s): Olli-Pekka Kilpi, Johannes Svensson, Jun Wu, Axel R. Persson, Reine Wallenberg, Erik Lind, Lars-Erik Wernersson
Published in: Nano Letters, Issue 17/10, 2017, Page(s) 6006-6010, ISSN 1530-6984
DOI: 10.1021/acs.nanolett.7b02251

High-Frequency Quantum Well InGaAs-on-Si MOSFETs With Scaled Gate Lengths

Author(s): Cezar B. Zota, Clarissa Convertino, Marilyne Sousa, Daniele Caimi, Kirsten Moselund, Lukas Czornomaz
Published in: IEEE Electron Device Letters, Issue 40/4, 2019, Page(s) 538-541, ISSN 0741-3106
DOI: 10.1109/led.2019.2902519

Demonstration of 3-D SRAM Cell by 3-D Monolithic Integration of InGaAs n-FinFETs on FDSOI CMOS With Interlayer Contacts

Author(s): Veeresh Deshpande, H. Hahn, E. O'Connor, Y. Baumgartner, D. Caimi, M. Sousa, H. Boutry, J. Widiez, L. Brevard, C. Le Royer, M. Vinet, J. Fompeyrine, L. Czornomaz
Published in: IEEE Transactions on Electron Devices, Issue 64/11, 2017, Page(s) 4503-4509, ISSN 0018-9383
DOI: 10.1109/ted.2017.2755662

DC and RF characterization of InGaAs replacement metal gate (RMG) nFETs on SiGe-OI FinFETs fabricated by 3D monolithic integration

Author(s): V. Deshpande, V. Djara, E. O'Connor, P. Hashemi, K. Balakrishnan, D. Caimi, M. Sousa, L. Czornomaz, J. Fompeyrine
Published in: Solid-State Electronics, Issue 128, 2017, Page(s) 87-91, ISSN 0038-1101
DOI: 10.1016/j.sse.2016.10.034

High-performance InGaAs FinFETs with raised source/drain extensions

Author(s): Clarissa Convertino, Cezar B. Zota, Daniele Caimi, Marilyne Sousa, Kirsten E. Moselund, Lukas Czornomaz
Published in: Japanese Journal of Applied Physics, Issue 58/8, 2019, Page(s) 080901, ISSN 0021-4922

High-Mobility GaSb Nanostructures Cointegrated with InAs on Si

Author(s): Mattias Borg, Heinz Schmid, Johannes Gooth, Marta D. Rossell, Davide Cutaia, Moritz Knoedler, Nicolas Bologna, Stephan Wirths, Kirsten E. Moselund, Heike Riel
Published in: ACS Nano, Issue 11/3, 2017, Page(s) 2554-2560, ISSN 1936-0851
DOI: 10.1021/acsnano.6b04541

Inversion in the In 0.53 Ga 0.47 As metal-oxide-semiconductor system: Impact of the In 0.53 Ga 0.47 As doping concentration

Author(s): É. O'Connor, K. Cherkaoui, S. Monaghan, B. Sheehan, I. M. Povey, P. K. Hurley
Published in: Applied Physics Letters, Issue 110/3, 2017, Page(s) 032902, ISSN 0003-6951
DOI: 10.1063/1.4973971

Impact of doping and diameter on the electrical properties of GaSb nanowires

Author(s): Aein S. Babadi, Johannes Svensson, Erik Lind, Lars-Erik Wernersson
Published in: Applied Physics Letters, Issue 110/5, 2017, Page(s) 053502, ISSN 0003-6951
DOI: 10.1063/1.4975374

Uniting III-V Tunnel FETs with Silicon

Author(s): Davide Cutaia, K. Moselund, H. Schmid, M. Borg, H. Riel
Published in: Compound Semiconductor, Issue 23 (1), 2017, Page(s) 38-42, ISSN 2042-7328

Three-dimensional monolithic integration of III-V and Si(Ge) FETs for hybrid CMOS and beyond

Author(s): V. Deshpande, V. Djara, E. O'Connor, P. Hashemi, T. Morf, K. Balakrishnan, D. Caimi, M. Sousa, J. Fompeyrine, L. Czornomaz
Published in: Japanese Journal of Applied Physics, Issue vol 56, 2017, Page(s) 04CA05, ISSN 1347-4065
DOI: 10.7567/JJAP.56.04CA05