Periodic Reporting for period 2 - ELENA (European electro-optic and nonlinear PIC platform based on lithium niobate)
Okres sprawozdawczy: 2023-07-01 do 2024-06-30
ELENA is set to transform the Photonic Integrated Circuit (PIC) industry with its innovative European LNOI platform. It aims to create the world's first open-access foundry for LNOI technology, providing advanced electro-optic and nonlinear capabilities. The project encompasses the entire supply chain, from producing 150 mm optical-grade LNOI wafers to high-yield foundry fabrication, PDK-based design software, and robust PIC packaging. This cost-effective open-access foundry, featuring a PDK library, will validate the technology through various prototypes for telecommunications, quantum technologies, and microwave photonics. The LNOI platform promises superior functionalities over a broad wavelength range, including high-speed electro-optic modulators, low-voltage switches, tunable resonators, lasers, and on-chip nonlinear wavelength conversion, benefiting fields such as quantum technology, telecommunications, LiDAR, and sensing.
In WP1, from the beginning of the project to the end of the reporting period, substantial progress has been made in building block design, simulation software development, and PDK designs. Key achievements include the successful design, fabrication, and testing of various passive and active building blocks, and the development of analytical and numerical models for nonlinear effects. Extensive testing has validated the designs, with new simulations addressing mismatches. Foundry-dedicated PDK building blocks were developed and integrated with layout tools, enabling effective optical system generation.
In WP2, in terms of LNOI substrate manufacturing we have developed recipes to deliver different generations with well-defined target stacks per generation. We have delivered wafers with LN thickness of 600 nm and we have done two rounds of BB fabrication on those wafers. On the PIC manufacturing side, we have conducted 4 full stacks RUN with an advanced layer stack with 3 waveguides and two metallization layers in the most recent RUN. We have delivered several chips to WP4 to measure BBs and early generation of the demonstrators. In parallel through dedicated etch test, metallization and deep grid short loops we have achieved a record average waveguide loss of 0.5 dB/cm, Rf loss of 10 dB/cm, and edge coupling efficiency of 3 dB per facet.
In WP3, we first designed optical-electrical co-packaging for TFLN-based integrated platform conceptually. Then we develop PWB technology to optically interface with TFLN edge couplers to reach insertion loss down to 2.18 dB. We developed the PCB for PIC testing and demonstration which enables external control of RF and DC lines.
Finally, in WP4, building block characterizations were done, and demonstrator designs submitted. Comparison between the measurement data and the simulation results provided an acceptable degree of coherence for the first generation of BBs. However, the observations revealed some issues: high RF losses (now solved in interaction with WP2), polarization mixing between TE and TM component (under investigations), and discrepancies between simulations and directional couplers measurement in terms of the splitting ratio and insertion loss. To address these issues, we have performed further tolerance study on the simulation considering the impacting parameters such as variation on the stack refractive indexes, waveguide sidewall angle, and etch depth variations issues. Consequently, we have initiated fabrication short loops with extensive parameter sweeps on each individual BB. For the demonstrators we have included sub-circuits in addition to the full circuitry to obtain as much as possible measurement data from the main blocks of the full circuit.
In terms of management (WP5), actions linked to monitoring of ELENA progress, organization of management meetings were continued while the first amendment, EC review and periodic reporting were completed.
In terms of communication and dissemination (WP6), the official project video presentation was publicly released and a joint technical workshop on heterogeneous integration was organised in April 2024 with sister projects, notably PATTERN Horizon Europe project.
In addition, several presentations were given in various conferences during the second half of 2023 (SPIE Photonics, CLEO…) and in 2024, and the catalogue of results was consolidated
In WP2, in terms of LNOI substrate manufacturing we have developed recipes to deliver different generations with well-defined target stacks per generation. We have delivered wafers with LN thickness of 600 nm and we have done two rounds of BB fabrication on those wafers. On the PIC manufacturing side, we have conducted 4 full stacks RUN with an advanced layer stack with 3 waveguides and two metallization layers in the most recent RUN. We have delivered several chips to WP4 to measure BBs and early generation of the demonstrators. In parallel through dedicated etch test, metallization and deep grid short loops we have achieved a record average waveguide loss of 0.5 dB/cm, Rf loss of 10 dB/cm, and edge coupling efficiency of 3 dB per facet.
In WP3, we first designed optical-electrical co-packaging for TFLN-based integrated platform conceptually. Then we develop PWB technology to optically interface with TFLN edge couplers to reach insertion loss down to 2.18 dB. We developed the PCB for PIC testing and demonstration which enables external control of RF and DC lines.
Finally, in WP4, building block characterizations were done, and demonstrator designs submitted. Comparison between the measurement data and the simulation results provided an acceptable degree of coherence for the first generation of BBs. However, the observations revealed some issues: high RF losses (now solved in interaction with WP2), polarization mixing between TE and TM component (under investigations), and discrepancies between simulations and directional couplers measurement in terms of the splitting ratio and insertion loss. To address these issues, we have performed further tolerance study on the simulation considering the impacting parameters such as variation on the stack refractive indexes, waveguide sidewall angle, and etch depth variations issues. Consequently, we have initiated fabrication short loops with extensive parameter sweeps on each individual BB. For the demonstrators we have included sub-circuits in addition to the full circuitry to obtain as much as possible measurement data from the main blocks of the full circuit.
In terms of management (WP5), actions linked to monitoring of ELENA progress, organization of management meetings were continued while the first amendment, EC review and periodic reporting were completed.
In terms of communication and dissemination (WP6), the official project video presentation was publicly released and a joint technical workshop on heterogeneous integration was organised in April 2024 with sister projects, notably PATTERN Horizon Europe project.
In addition, several presentations were given in various conferences during the second half of 2023 (SPIE Photonics, CLEO…) and in 2024, and the catalogue of results was consolidated
WP1 aims to design high-performance building blocks for photonic integrated circuits, develop a user-friendly simulation tool, and create PDKs for circuit-level design on the TFLN platform. So far, WP1 has completed the design, fabrication, and initial testing of various building blocks, including waveguides, MMIs, directional couplers, grating couplers, and Y splitters. The PDKs and layouts for end-users have also been finalized which is beyond the state of the art.
As part of WP2, ELENA consortium has developed the first open-access foundry for TFLN PICs in the world, and demonstrated TFLN BBs fabricated on European LNOI substrates for the first time. ELENA practices to set MPW scheme with an average cycle time of 7 month, in a short period of time are comparable with the mainstream PIC platforms. Until the end of the project, the consortium expects to further stabilize the technology steps to be able to exploit ELENA results in a format of a reliable LNOI substrate supplier and open-access foundry service for the whole PIC community.
In WP3 we have interfaced an LNOI chip with a single mode fiber using photonic wire bonding. Such integration is beyond the state of the art for a standardized platform using PDK building block for the edge coupling and photonic wire bonding for such a polish-less chip facet.
Finally, ELENA has developed under WP4 the most advanced TFLN PIC stack to date, incorporating multiple technological steps such as three waveguides, two metallization layers, cladding, and clad opening. This advancement allows for the implementation of sophisticated prototype circuits in our RUNs. However, we are encountering challenges such as high RF losses, partly due to the cladding deposition method. Additionally, material modifications during deposition appear to affect the effective index of refraction. Despite these issues, the consortium remains committed to including cladding in the process. Literature surveys indicate that many demonstrations have been published without cladding, which limits architectural complexity (e.g. no metal crossing) and potentially reduces chip lifespan due to a lack of contamination protection. This presents an unforeseen advantage for the ELENA platform compared to the state of the art. This will facilitate the platform's adoption for large component on-chip applications and potentially for large-scale manufacturing of integrated systems in emerging domains such as AI, quantum computing, and neuromorphic computing.
As part of WP2, ELENA consortium has developed the first open-access foundry for TFLN PICs in the world, and demonstrated TFLN BBs fabricated on European LNOI substrates for the first time. ELENA practices to set MPW scheme with an average cycle time of 7 month, in a short period of time are comparable with the mainstream PIC platforms. Until the end of the project, the consortium expects to further stabilize the technology steps to be able to exploit ELENA results in a format of a reliable LNOI substrate supplier and open-access foundry service for the whole PIC community.
In WP3 we have interfaced an LNOI chip with a single mode fiber using photonic wire bonding. Such integration is beyond the state of the art for a standardized platform using PDK building block for the edge coupling and photonic wire bonding for such a polish-less chip facet.
Finally, ELENA has developed under WP4 the most advanced TFLN PIC stack to date, incorporating multiple technological steps such as three waveguides, two metallization layers, cladding, and clad opening. This advancement allows for the implementation of sophisticated prototype circuits in our RUNs. However, we are encountering challenges such as high RF losses, partly due to the cladding deposition method. Additionally, material modifications during deposition appear to affect the effective index of refraction. Despite these issues, the consortium remains committed to including cladding in the process. Literature surveys indicate that many demonstrations have been published without cladding, which limits architectural complexity (e.g. no metal crossing) and potentially reduces chip lifespan due to a lack of contamination protection. This presents an unforeseen advantage for the ELENA platform compared to the state of the art. This will facilitate the platform's adoption for large component on-chip applications and potentially for large-scale manufacturing of integrated systems in emerging domains such as AI, quantum computing, and neuromorphic computing.