During the first 36 months of the project, the PI together with her team focused on the “Foundational building blocks”, which is phase 1 of the project. Month 36 is the end of WP1 - End Node, WP2 – Computational Complexity, WP3 – HW/SW interface: flexibility versus performance, and WP4 – Design of core accelerator. Partial results are also available for phase 2, ‘the stepwise integration’. Phase 3 recently started (M31).
Computing on encrypted data means that the sensitive data is encrypted at the user’s side, which we call the end-nodes. The encrypted data is next sent on the internet, or stored on a remote server, which we assume is untrusted. The topics we started during this first period are the following:
• At the user’s end, sensitive data needs to be encrypted, and the results of the operations decrypted. The challenge here is that the encryption and decryption operations occur potentially in insecure environments, so these hardware implementations need protection against side-channel and fault attacks. In this first period, we focused on masking, a particular protection mechanism, to protect lattice-based encryption schemes against side-channel and fault attacks. This work is part of WP1. We have results both on the attack side, as well as on the protection side.
Some highlights are:
[Higher-Order Masked Saber.
https://doi.org/10.1007/978-3-031-14791-3_5](odnośnik otworzy się w nowym oknie) Google Scholar: 34 citations
[C. Mujdei, L. Wouters, A. Karmakar, A. Beckers, J. Bermudo Mera, I. Verbauwhede (2024): Side-channel Analysis of Lattice-based Post-quantum Cryptography: Exploiting Polynomial Multiplication. ACM Trans. Embed. Comput. Syst. 23(2): 27:1-27:23 (2024).] Measuring impact: this paper has already 71 citations on Google Scholar.
• Making applications Computing on Encrypted Data (COED) friendly is a big challenge. In a first experiment, we studied the quantization effect on neural networks to make them more FHE-friendly. This work is part of WP2.
• A major result of the first phase is our FPT processor. This is a domain-specific accelerator suitable for an FPGA platform. It focuses on the programmable bootstrapping step of the Torus Fully Homomorphic Encryption (TFHE). It is designed under WP3 and WP4.
This FPT processor is part of IP transfer that will be transferred from KU Leuven to the spinoff company Belfort Labs.
WP5 and WP6 recently started:
In the context of WP5, we have first results making a distance calculation application FHE friendly. It is currently submitted to a major security conference. Its pre-print is available through IACR eprint. On the technology developed in this work, a patent application has been filed.
In the contecxt of WP6, we are experimenting with designs to fit on multiple FPGA, addressing the parallelism challenges.
This work will be presented at CHES in September 2025:
WP7 also recently started. In WP7, an end-to-end application is developed. We start from real-life use cases, such as the above mentioned Leuvensthein. We will investigate if Leuvensthein is also suitable for DNA matching applications. Other applications being considered are privacy friendly machine learning.
