Pilot using Independent Local & Open Technologies

CORDIS oferuje możliwość skorzystania z odnośników do publicznie dostępnych publikacji i rezultatów projektów realizowanych w ramach programów ramowych HORYZONT.

Odnośniki do rezultatów i publikacji związanych z poszczególnymi projektami 7PR, a także odnośniki do niektórych konkretnych kategorii wyników, takich jak zbiory danych i oprogramowanie, są dynamicznie pobierane z systemu OpenAIRE .

Rezultaty

Refined parallel Programming Interfaces

D7.3. Refined parallel Programming Interfaces (FORTH, O, PU) [M30]. This document will elaborate on D7.1 based on the experience and results in D7.2. It will also provide results for the updated version of the implementations in D7.2.

Compilation and Emulation infrastructure

D9.1. Compilation and Emulation infrastructure (BSC, O, PU) [M9]. This deliverable will provide an updated version of the EPI compilation and Emulation infrastructure (Vehave) extended to support v1.0 of the RISC-V ISA. It will support C/C++ and will include automatic vectorization capabilities.

Software and system integration specification and requirements

D10.5 Software and system integration specification and requirements (BSC,R, PU) (M6). Working with a software/hardware co-design approach, this deliverable will provide architectural requirements extracted from the following applications: EC-Earth and GROMACS HPC applications, BLAS, FFTW and stencil numerical HPC kernels, image processing and deep learning applications as well as the molecular dynamics application utilizing both HPC and deep learning kernels.

First Dissemination and Communication Report

D2.2: First Dissemination and Communication Report (BSC, R, PU) [M12] This deliverable will report on the dissemination and communication activities of the project done in the first year.

Collaboration roadmap and collaboration agreement with EUPEX

D35 Collaboration roadmap and collaboration agreement with EUPEX EUPEX aims at delivering a largescale modular demonstrator based on the ARMbased general purpose processor design under development in EPI In contrast the European PILOT will deliver a demonstrator based on the RISCV accelerators in EPI The European PILOT output could be integrated as an additional module into the EUPEX modular supercomputer For this reason we will define a collaboration roadmap between the two pilots to ensure the integration of the two projects into a global framework A joint Collaboration Agreement will be signed to that effect

Parallel Programming Runtimes specifications

D71 Parallel Programming Runtimes specifications BSC R PU M6 This deliverable will define the functionalities and interfaces that will have to be integrated in the Pilot Beyond the basic MPI and OpenMP support based in MPICH and the LLVM OpenMP runtime it will include the TAMPI interface for improved interoperability between MPI and OpenMP resulting in more productive mechanisms to achieve communicationcomputation overlap Also the DLB interfaces to dynamically reassign cores between OpenMP threads in different processes The document will specify the fine grain resource management policies to be implemented by these runtimes within the processes and at the node level as well as the vertical interface to the coarser grain schedulers in WP5 It will also specify the optimizations to be implemented in the internals of the runtime like vectorization offloading to communication devices as well as mechanisms to be used to minimize the impact of noise OS communications in performance

Design of AI frameworks for the Pilot platform

D61 Design of AI frameworks for the Pilot platform ETH R PU M6 This deliverable will present the design of the AI frameworks ONNXDaCe TensorFlow Tarantela for accelerated ONNXDaCe TF and distributed Tarantella learning taking into account the requirements of the respective WP1 verticals

Architecture specification and requirements for the MLS compute tile

D10.2 Architecture specification and requirements for the MLS compute tile (ETH, R, PU) (M6). This deliverable will provide the architecture specification of the Machine Learning and Stencil (MLS) compute tile.

Refined System Software components architecture

D8.3. Refined System Software components architecture (CINI, R, PU) [M30]. This report will detail, based on the experience reported in D8.2. and the detailed knowledge of the actual design resulting from Stream 3 will refine the specification and architecture of the File system and Resource management high level system software components to be implemented on the actual Pilot.

System Software components architecture

D8.1. System Software components architecture (BSC, R, PU) [M6]. This deliverable will describe the functionality and interfaces of the File System and Global Resource Management components that will be provided to submit and execute workloads to the system. For general functionalities adopted from standards of existing developments, the document will refer to the appropriate external documentation. New features defined in this task (e.g. integration of the components) will be described. The document will also describe the global architecture of the implementation.

Dissemination and Communication Plan

D21 Dissemination and Communication Plan BSC R PU M3 This deliverable will set out the dissemination and communication strategy and the activities to be undertaken to achieve it Results of the dissemination work will be reported in the periodic and final reports

Project Management and Quality Guidelines

Data Management Plan

Publikacje

TOP: Towards Open & Predictable Heterogeneous SoCs

Autorzy: Luca Valente, Francesco Restuccia, Davide Rossi, Ryan Kastner, Luca Benini
Opublikowane w: IEEE Transactions on Computers, Numer 73, 2024, Strona(/y) 2678-2692, ISSN 0018-9340
Wydawca: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tc.2024.3441849

Processor simulation as a tool for performance engineering

Autorzy: Carlos Falquez, Shiting Long, Nam Ho, Estela Suarez, Dirk Pleiter
Opublikowane w: Frontiers in High Performance Computing, Numer 3, 2026, ISSN 2813-7337
Wydawca: Frontiers Media SA
DOI: 10.3389/fhpcp.2025.1669101

Modeling and Controlling Many-Core HPC Processors: An Alternative to PID and Moving Average Algorithms

Autorzy: Giovanni Bambini, Alessandro Ottaviano, Christian Conficoni, Andrea Tilli, Luca Benini, Andrea Bartolini
Opublikowane w: ACM Transactions on Autonomous and Adaptive Systems, Numer 21, 2026, Strona(/y) 1-32, ISSN 1556-4665
Wydawca: Association for Computing Machinary, Inc.
DOI: 10.1145/3694687

A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks

Autorzy: Angelo Garofalo; Geethan Karunaratne; Francesco Conti; DAVIDE ROSSI; Irem Boybat; GIANMARCO OTTAVI; LUCA BENINI
Opublikowane w: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Numer 1, 2022, ISSN 2156-3357
Wydawca: IEEE Circuits and Systems Society
DOI: 10.1109/jetcas.2022.3170152

Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters

Autorzy: Jie Chen; Igor Loi; Eric Flamand; Giuseppe Tagliavini; Luca Benini; Davide Rossi
Opublikowane w: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 31 (4), Numer 8, 2023, ISSN 1557-9999
Wydawca: IEEE
DOI: 10.1109/tvlsi.2022.3228336

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET

Autorzy: Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
Opublikowane w: IEEE Journal of Solid-State Circuits, Numer 60, 2025, Strona(/y) 1324-1338, ISSN 0018-9200
Wydawca: Institute of Electrical and Electronics Engineers
DOI: 10.1109/jssc.2025.3529249

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation

Autorzy: Ottaviano, A., Balas, R., Bambini, G. et al
Opublikowane w: International Journal of Parallel Programming, 2024, ISSN 1573-7640
Wydawca: Springer
DOI: 10.1007/s10766-024-00761-4

Reliability-oriented resource management for High-Performance Computing

Autorzy: Giuseppe Massari, Miriam Peta, Alessandro Campi, Federico Reghenzani, Federico Terraneo, Giovanni Agosta, William Fornaciari, Sebastian Ciesielski, Michal Kulczewski, Wojciech Piatek
Opublikowane w: Sustainable Computing: Informatics and Systems, Numer 39, 2025, Strona(/y) 100873, ISSN 2210-5379
Wydawca: Elsevier USA
DOI: 10.1016/j.suscom.2023.100873

Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

Autorzy: Gianmarco Ottavi; Angelo Garofalo; Giuseppe Tagliavini; Francesco Conti; Alfio Di Mauro; Luca Benini; Davide Rossi
Opublikowane w: IEEE Transactions on Circuits and Systems I: Regular Papers, 70 (6), Numer 8, 2023, ISSN 1558-0806
Wydawca: IEEE
DOI: 10.1109/tcsi.2023.3254810

Synergizing OpenMP Paradigms Through Free Agents and nOS-V

Autorzy: Antoni Navarro, Raúl Peñacoba, Vincent A. Arcila, Rodrigo Arias, David Álvarez, Vicenç Beltran
Opublikowane w: SN Computer Science, Numer 6, 2025, ISSN 2661-8907
Wydawca: Springer Science and Business Media LLC
DOI: 10.1007/s42979-025-04406-2

Darkside: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training

Autorzy: Angelo Garofalo; Yvan Tortorella; Matteo Perotti; Luca Valente; Alessandro Nadalini; Luca Benini; Davide Rossi; Francesco Conti
Opublikowane w: IEEE Open Journal of the Solid-State Circuits Society, Numer 1, 2022, ISSN 2644-1349
Wydawca: IEEE
DOI: 10.1109/ojsscs.2022.3210082

Optimizing Foundation Model Inference on a Many-Tiny-Core Open-Source RISC-V Platform

Autorzy: Viviane Potocnik, Luca Colagrande, Tim Fischer, Luca Bertaccini, Daniele Jahier Pagliari, Alessio Burrello, Luca Benini
Opublikowane w: IEEE Transactions on Circuits and Systems for Artificial Intelligence, Numer 1, 2024, Strona(/y) 37-52, ISSN 2996-6647
Wydawca: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/tcasai.2024.3459412

Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra

Autorzy: Paul Scheffler; Florian Zaruba; Fabian Schuiki; Torsten Hoefler; Luca Benini
Opublikowane w: IEEE Transactions on Parallel and Distributed Systems, 2023, ISSN 1558-2183
Wydawca: IEEE
DOI: 10.1109/tpds.2023.3322029

DNN Is Not All You Need: Parallelizing Non-neural ML Algorithms on Ultra-low-power IoT Processors

Autorzy: Enrico Tabanelli, Giuseppe Tagliavini, Luca Benini
Opublikowane w: ACM Transactions on Embedded Computing Systems, Numer 22, 2025, Strona(/y) 1-33, ISSN 1539-9087
Wydawca: Association for Computing Machinary, Inc.
DOI: 10.1145/3571133

Inference performance of large language models on a 64-core RISC-V CPU with silicon-enabled vectors

Autorzy: Adriano Marques Garcia, Giulio Malenza, Robert Birke, Marco Aldinucci
Opublikowane w: Future Generation Computer Systems, Numer 177, 2026, Strona(/y) 108242, ISSN 0167-739X
Wydawca: Elsevier BV
DOI: 10.1016/j.future.2025.108242

Taming Offload Overheads in a Massively Parallel Open-Source RISC-V MPSoC: Analysis and Optimization

Autorzy: Luca Colagrande, Luca Benini
Opublikowane w: IEEE Transactions on Parallel and Distributed Systems, Numer 36, 2025, Strona(/y) 1193-1205, ISSN 1045-9219
Wydawca: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tpds.2025.3555718

MPI malleability validation under replayed real-world HPC conditions

Autorzy: Sergio Iserte, Maël Madon, Georges Da Costa, Jean-Marc Pierson, Antonio J. Peña
Opublikowane w: Future Generation Computer Systems, Numer 178, 2026, Strona(/y) 108305, ISSN 0167-739X
Wydawca: Elsevier BV
DOI: 10.1016/j.future.2025.108305

Fatigue and adherence can challenge the prevailing wisdom on the response to severe epidemic outbreaks

Autorzy: Piero Manfredi, Marco Laurino, Giulio Pisaneschi, Alberto Landi
Opublikowane w: Journal of the Royal Society Interface, Numer 23, 2026, ISSN 1742-5662
Wydawca: The Royal Society
DOI: 10.1098/rsif.2025.0287

FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic

Autorzy: Tim Fischer, Michael Rogenmoser, Matheus Cavalcante, Frank K. Gürkaynak, Luca Benini
Opublikowane w: IEEE Design & Test, Numer 40, 2023, Strona(/y) 7-17, ISSN 2168-2356
Wydawca: IEEE Computer Society
DOI: 10.1109/mdat.2023.3306720

Edge HPC Architectures for AI-Based Video Surveillance Applications

Autorzy: Federico Rossi, Sergio Saponara
Opublikowane w: Electronics, Numer 13, 2025, Strona(/y) 1757, ISSN 2079-9292
Wydawca: MDPI AG
DOI: 10.3390/electronics13091757

MiniFloats on RISC-V Cores: ISA Extensions with Mixed-Precision Short Dot Products

Autorzy: L. Bertaccini, G. Paulin, M. Cavalcante, T. Fischer, S. Mach and L. Benini
Opublikowane w: IEEE Transactions on Emerging Topics in Computing, 2024, ISSN 2168-6750
Wydawca: IEEE Computer Society
DOI: 10.1109/tetc.2024.3365354

A Robust and Portable All-Digital TRNG Circuit for Extending the Instruction Set Architecture of RISC-V Processors

Autorzy: Luca Crocetti, Ettore Noccetti, Pietro Nannipieri, Stefano Di Matteo, Ivan Sarno, Sergio Saponara
Opublikowane w: IEEE Access, Numer 13, 2025, Strona(/y) 201741-201749, ISSN 2169-3536
Wydawca: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/access.2025.3638434

Analysis of Model Parallelism for AI Applications on a 64-core RV64 Server CPU

Autorzy: Giulio Malenza, Adriano Marques Garcia, Robert Birke, Luca Benini, Marco Aldinucci
Opublikowane w: International Journal of Parallel Programming, Numer 53, 2025, ISSN 0885-7458
Wydawca: Kluwer Academic Publishers
DOI: 10.1007/s10766-025-00802-6

FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic

Autorzy: Tim Fischer; Michael Rogenmoser; Matheus Cavalcante; Frank K. Gürkaynak; Luca Benini
Opublikowane w: IEEE Design&Test, 2023, ISSN 2168-2364
Wydawca: IEEE
DOI: 10.3929/ethz-b-000638546

FlooNoC: A 645-Gb/s/link 0.15-pJ/B/hop Open-Source NoC With Wide Physical Links and End-to-End AXI4 Parallel Multistream Support

Autorzy: Tim Fischer, Michael Rogenmoser, Thomas Benz, Frank K. Gürkaynak, Luca Benini
Opublikowane w: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Numer 33, 2025, Strona(/y) 1094-1107, ISSN 1063-8210
Wydawca: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tvlsi.2025.3527225

A High-performance, Energy-efficient Modular DMA Engine Architecture

Autorzy: Benz, Thomas, Rogenmoser, Michael, Scheffler, Paul, Riedel, Samuel, Ottaviano, Alessandro, Kurth, Andreas, Hoefler, Torsten, Benini, Luca
Opublikowane w: IEEE Transactions on Computers, 2024, ISSN 1557-9956
Wydawca: IEEE
DOI: 10.1109/tc.2023.3329930

Meet Monte Cimone: exploring RISC-V high performance compute clusters

Autorzy: Federico Ficarelli, Andrea Bartolini, Emanuele Parisi, Francesco Beneventi, Francesco Barchi, Daniele Gregori, Fabrizio Magugliani, Marco Cicala, Cosimo Gianfreda, Daniele Cesarini, Andrea Acquaviva and Luca Benini
Opublikowane w: 2022
Wydawca: ACM
DOI: 10.1145/3528416.3530869

ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration

Autorzy: Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Antonio del Vecchio, Maicol Ciani, Davide Rossi, Luca Benini, Andrea Bartolini
Opublikowane w: Embedded Computer Systems: Architectures, Modeling, and Simulation - Lecture Notes in Computer Science (SAMOS22), 2022, Strona(/y) 120-135, ISBN 978-3-031-15073-9
Wydawca: Springer
DOI: 10.1007/978-3-031-15074-6_8

A Priori Loop Nest Normalization: Automatic Loop Scheduling in Complex Applications

Autorzy: Lukas Trümper, Philipp Schaad, Berke Ates, Alexandru Calotoiu, Marcin Copik, Torsten Hoefler
Opublikowane w: Proceedings of the 23rd ACM/IEEE International Symposium on Code Generation and Optimization, 2025, Strona(/y) 418-430
Wydawca: ACM
DOI: 10.1145/3696443.3708951

Distributed Edge Inference: an Experimental Study on Multiview Detection

Autorzy: Gianluca Mittone, Giulio Malenza, Marco Aldinucci, Robert Birke
Opublikowane w: Proceedings of the IEEE/ACM 16th International Conference on Utility and Cloud Computing, 2025, Strona(/y) 1-6
Wydawca: ACM
DOI: 10.1145/3603166.3632561

STen: An Interface for Efficient Sparsity in PyTorch

Autorzy: A. Ivanov, N. Dryden, T. Hoefler
Opublikowane w: Sparsity in Neural Networks workshop 2022, 2022
Wydawca: ETH Zurich, Scalable Parallel Computing Laboratory
DOI: 10.48550/arxiv.2304.07613

Experimenting with Emerging RISC-V Systems for Decentralised Machine Learning

Autorzy: Gianluca Mittone, Nicolò Tonci, Robert Birke, Iacopo Colonnelli, Doriana Medić, Andrea Bartolini, Roberto Esposito, Emanuele Parisi, Francesco Beneventi, Mirko Polato, Massimo Torquati, Luca Benini, Marco Aldinucci
Opublikowane w: 2023
Wydawca: ACM
DOI: 10.48550/arxiv.2302.07946

Bridging the Gap Between Genericity and Programmability of Dynamic Resources in HPC

Autorzy: Dominik Huber, Sergio Iserte, Martin Schreiber, Antonio J. Peña, Martin Schulz
Opublikowane w: ISC High Performance 2025 Research Paper Proceedings (40th International Conference), 2025, Strona(/y) 1-11
Wydawca: IEEE
DOI: 10.23919/isc.2025.11018304

Benchmarking Federated Learning Frameworks for Medical Imaging Tasks

Autorzy: Fonio, S.
Opublikowane w: Image Analysis and Processing - ICIAP 2023 Workshops. ICIAP 2023. Lecture Notes in Computer Science, 2024, ISBN 978-3-031-51026-7
Wydawca: Springer Nature
DOI: 10.1007/978-3-031-51026-7_20

The Italian research on HPC key technologies across EuroHPC

Autorzy: Marco Aldinucci, Giovanni Agosta, Antonio Andreini, Claudio A Ardagna, Andrea Bartolini, Alessandro Cilardo, Biagio Cosenza, Marco Danelutto, Roberto Esposito, William Fornaciari, Roberto Giorgi, Davide Lengani, Raffaele Montella, Mauro Olivieri, Sergio Saponara, Daniele Simoni, Massimo Torquati
Opublikowane w: 2021
Wydawca: ACM
DOI: 10.1145/3457388.3458508

I/O-Optimal Cache-Oblivious Sparse Matrix-Sparse Matrix Multiplication

Autorzy: Niels Gleinig, Maciej Besta, Torsten Hoefler
Opublikowane w: 36th IEEE Interational Parallel and Distributed Processing Symposium, 2022, ISBN 978-1-6654-8106-9
Wydawca: 2022 IEEE International Parallel and Distributed Processing Symposium (IPDPS)

The Red-Blue Pebble Game on Trees and DAGs with Large Input

Autorzy: Niels Gleinig, Torsten Hoefler
Opublikowane w: Structural Information and Communication Complexity. SIROCCO 2022, Lecture Notes in Computer Science, 2022, Strona(/y) 135-153, ISBN 978-3-031-09992-2
Wydawca: Springer, Cham
DOI: 10.1007/978-3-031-09993-9_8

Specialization meets Flexibility: a Heterogeneous Architecture for High-Efficiency, High-flexibility AR/VR Processing

Autorzy: Arpan Suravi Prasad; Luca Benini; Francesco Conti
Opublikowane w: 2023 60th ACM/IEEE Design Automation Conference (DAC), 2023, ISBN 979-8-3503-2348-1
Wydawca: IEEE
DOI: 10.1109/dac56929.2023.10247945

Lifting C Semantics for Dataflow Optimization

Autorzy: Alexandru Calotoiu, Tal Ben-Nun,Grzegorz Kwasniewski, Johannes de Fine Licht, Timo Schneider, Philipp Schaad, Torsten Hoefler
Opublikowane w: ICS '22: Proceedings of the 36th ACM International Conference on Supercomputing, 2022
Wydawca: ICS '22: Proceedings of the 36th ACM International Conference on Supercomputing
DOI: 10.1145/3524059.3532389

RIVETS: an efficient training and inference library for RISC-V with snitch extensions

Autorzy: Ivanov, Andrei, Timo Schneider, Luca Benini, and Torsten Hoefler
Opublikowane w: 2023
Wydawca: RISC-V Summit Europe, Barcelona

A Federated Learning Benchmark for Drug-Target Interaction

Autorzy: Gianluca Mittone; Filip Svoboda; Marco Aldinucci; Nicholas Lane; Pietro Lió
Opublikowane w: In Companion Proceedings of the ACM Web Conference 2023 (WWW '23 Companion), 2023, ISBN 978-1-4503-9419-2
Wydawca: ACM DL
DOI: 10.1145/3543873.3587687

Enhanced LPDDR4X PHY in 12 nm FinFET

Autorzy: Johannes Feldmann, Jan Lappas, Mohammadreza Esmaeilpour, Hussien Abdo, Christian Weis, Norbert Wehn
Opublikowane w: 2025
Wydawca: Cornell University (arXiv)
DOI: 10.48550/arxiv.2503.11654

Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores

Autorzy: Luca Colagrande, Luca Benini
Opublikowane w: 2025 62nd ACM/IEEE Design Automation Conference (DAC), 2025, Strona(/y) 1-7
Wydawca: IEEE
DOI: 10.1109/dac63849.2025.11132520

MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores

Autorzy: Bertaccini, Luca; Paulin, Gianna; Fischer, Tim; Mach, Stefan; Benini, Luca
Opublikowane w: 2022 IEEE 29th Symposium on Computer Arithmetic (ARITH), Numer 5, 2022
Wydawca: IEEE
DOI: 10.1109/arith54963.2022.00010

SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers

Autorzy: Paul Scheffler, Luca Colagrande, Luca Benini
Opublikowane w: Proceedings of the 61st ACM/IEEE Design Automation Conference, 2025, Strona(/y) 1-6
Wydawca: ACM
DOI: 10.1145/3649329.3658494

OSMOSIS: Enabling Multi-Tenancy in Datacenter SmartNIC

Autorzy: Khalilov, M., Chrapek, M., Shen, S., Vezzu, A., Benz, T., Di Girolamo, S., ... & Hoefler, T.
Opublikowane w: 2024, Strona(/y) 247-263
Wydawca: USENIX ATC

Dallmi: Domain adaption for llm-based multi-label classifier

Autorzy: M. Betianu, A. Malan, M. Aldinucci, R. Birke, and L. Y. Chen
Opublikowane w: Advances in Knowledge Discovery and Data Mining - 28th Pacific-Asia Conference on Knowledge Discovery and Data Mining, PAKDD 2024, Lecture Notes in Computer Science, 2024, ISBN 978-981-97-2259-4
Wydawca: Springer
DOI: 10.1007/978-981-97-2259-4_21

Model-Agnostic Federated Learning

Autorzy: Gianluca Mittone; Walter Riviera; Iacopo Colonnelli; Robert Birke; Marco Aldinucci
Opublikowane w: Euro-Par 2023: Parallel Processing, Lecture Notes in Computer Science, Numer 3, 2023, Strona(/y) 383-396, ISBN 978-3-031-39698-4
Wydawca: Springer Nature
DOI: 10.1007/978-3-031-39698-4_26

Federated Learning meets HPC and cloud

Autorzy: Iacopo Colonnelli, Bruno Casella, Gianluca Mittone, Yasir Arfat, Barbara Cantalupo, Roberto Esposito, Alberto Riccardo Martinelli, Doriana Medic, Marco Aldinucci
Opublikowane w: 2022, Strona(/y) 193-199, ISBN 978-3-031-34167-0
Wydawca: Springer
DOI: 10.1007/978-3-031-34167-0_39

AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads

Autorzy: Chi Zhang; Paul Scheffler; Thomas Benz; Matteo Perotti; Luca Benini
Opublikowane w: 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023, ISBN 979-8-3503-9624-9
Wydawca: IEEE
DOI: 10.23919/date56975.2023.10137243

Benchmarking FedAvg and FedCurv for Image Classification Tasks

Autorzy: Bruno Casella, Roberto Esposito, Carlo Cavazzoni, Marco Aldinucci
Opublikowane w: The 1st Italian Conference on Big Data and Data Science, 2022, Strona(/y) 99-100
Wydawca: CEUR-WS
DOI: 10.48550/arxiv.2303.17942

Efficient Quantized Sparse Matrix Operations on Tensor Cores

Autorzy: Shigang Li; Kazuki Osawa; Torsten Hoefler
Opublikowane w: SC '22: Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis, 2022, Strona(/y) 1-15, ISBN 978-1-6654-5444-5
Wydawca: IEEE
DOI: 10.1109/sc41404.2022.00042

Exploring and Exploiting Data-Free Model Stealing

Autorzy: Chi Hong, Jiyue Huang, Robert Birke, Lydia Y. Chen
Opublikowane w: Proceedings of the European Conference on Machine Learning and Principles and Practice of Knowledge Discovery in Databases 2023, 2023, Strona(/y) 20-35, ISBN 978-3-031-43424-2
Wydawca: Springer Nature
DOI: 10.1007/978-3-031-43424-2_2

ILAN: The Interference- and Locality-Aware NUMA Scheduler

Autorzy: Edvin Mellberg, Axel Carlsson, Jing Chen, Miquel Pericàs
Opublikowane w: Proceedings of the SC '25 Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis, 2026, Strona(/y) 1544-1553
Wydawca: ACM
DOI: 10.1145/3731599.3767701

Boosting the Federation: Cross-Silo Federated Learning without Gradient Descent

Autorzy: Mirko Polato; Roberto Esposito; Marco Aldinucci
Opublikowane w: Proceedings of the International Joint Conference on Neural Networks (IJCNN 2022), 2022, Strona(/y) 1-10, ISBN 978-1-7281-8671-9
Wydawca: IEEE
DOI: 10.1109/ijcnn55064.2022.9892284

Efficient Direct Convolution Using Long SIMD Instructions

Autorzy: Alexandre de Limas Santana; Adrià Armejach; Marc Casas
Opublikowane w: PPoPP '23: Proceedings of the 28th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming, 2023, Strona(/y) 342-353, ISBN 979-84-00-70015-6
Wydawca: ACM DL
DOI: 10.1145/3572848.3577435

Fast Arbitrary Precision Floating Point on FPGA

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