Periodic Reporting for period 1 - INSPIRE (Innovating iN Smart Programmable IntegRatEd photonics)
Okres sprawozdawczy: 2022-04-01 do 2023-03-31
"iPronics has pioneered Field Programmable Photonic Gate Arrays (FPPGA), an entirely new class of powerful, flexible photonic processors for computing applications in the optical sphere. Unlike electronic FPGAs, they use optical interference to perform very high-speed analog operations. This delivers major increases in system performance and reduced power consumption.
INSPIRE project will make FPPGA programmable photonics available in form of TRL5/6 demonstrators for the first time by increasing the number of programmable unit cells per chip and improving key performance characteristics including power consumption, space requirements and chip coupling losses.
The main objectives of INSPIRE project are:
1. To capture, evaluate and integrate specific end user requirements regarding programmable photonic processors into our product development,
2. to develop the technical foundations of a solution that will meet these requirements (optical layer, auxiliary electronics, software suite), and
3. to validate the advancement of this solution on the current state-of-the-art in the form of fully functional TRL6 demonstrators for three selected market verticals."
INSPIRE project will make FPPGA programmable photonics available in form of TRL5/6 demonstrators for the first time by increasing the number of programmable unit cells per chip and improving key performance characteristics including power consumption, space requirements and chip coupling losses.
The main objectives of INSPIRE project are:
1. To capture, evaluate and integrate specific end user requirements regarding programmable photonic processors into our product development,
2. to develop the technical foundations of a solution that will meet these requirements (optical layer, auxiliary electronics, software suite), and
3. to validate the advancement of this solution on the current state-of-the-art in the form of fully functional TRL6 demonstrators for three selected market verticals."
During the first year of INSPIRE project the work performed in the different Work Packages and the achieved results are the following ones:
WP1: Design and simulation of different optical building blocks such as directional couplers, Multimode Interferometers (MMIs) topological optimization, and Standard MMIs. With the design and simulation of these building blocks, two different layouts of Photonic Integrated Circuit have been designed, one called MAIN and the other COMPUTING, being the main difference between them the high performance building blocks that are included and the size. These two layouts have been manufactured in AMF foundry and chips have been measured being now the first physical specimens of chips available at iPronics.
WP2: Development of the driving unit has been finished, being this unit the one providing electrical pulses to the optical chip to configure it in the appropriate way. The first version of the monitoring unit development has been also finished, being this unit the one reading the outputs of the PIC and sharing the information with the Logic Unit. Additionally, a market analysis and selection of the most appropriate Thermo-electric controller has been performed and the first validations of a new integrated laser have started. In parallel, the development of a Motherboard using Flip-Chip approach is on-going
WP3: In the software layer, development of APIs for the integration of all the subsystems inside the iPronics system has been performed. Apart from that, a system emulator has been created including the definition of different specific application notebooks. In the last 4 months, the development of high-level libraries has been started and it is an on-going task
WP4: Inside this WP, the Besta testing program has been launched, that has allowed to identify potential adopters and engage them. The first specifications for our PIC have been defined considering the requirements from the potential adopters that have been identified.
WP5: The work performed in this WP has been mainly the development of the iPronics website and marketing material such as the first iPronics booklet used to highlight the main application in which the iPronics system can be used and the first attendance with a booth to an International Trade Show, the OFC 2023."
WP1: Design and simulation of different optical building blocks such as directional couplers, Multimode Interferometers (MMIs) topological optimization, and Standard MMIs. With the design and simulation of these building blocks, two different layouts of Photonic Integrated Circuit have been designed, one called MAIN and the other COMPUTING, being the main difference between them the high performance building blocks that are included and the size. These two layouts have been manufactured in AMF foundry and chips have been measured being now the first physical specimens of chips available at iPronics.
WP2: Development of the driving unit has been finished, being this unit the one providing electrical pulses to the optical chip to configure it in the appropriate way. The first version of the monitoring unit development has been also finished, being this unit the one reading the outputs of the PIC and sharing the information with the Logic Unit. Additionally, a market analysis and selection of the most appropriate Thermo-electric controller has been performed and the first validations of a new integrated laser have started. In parallel, the development of a Motherboard using Flip-Chip approach is on-going
WP3: In the software layer, development of APIs for the integration of all the subsystems inside the iPronics system has been performed. Apart from that, a system emulator has been created including the definition of different specific application notebooks. In the last 4 months, the development of high-level libraries has been started and it is an on-going task
WP4: Inside this WP, the Besta testing program has been launched, that has allowed to identify potential adopters and engage them. The first specifications for our PIC have been defined considering the requirements from the potential adopters that have been identified.
WP5: The work performed in this WP has been mainly the development of the iPronics website and marketing material such as the first iPronics booklet used to highlight the main application in which the iPronics system can be used and the first attendance with a booth to an International Trade Show, the OFC 2023."
Expected results until the end of the project are related to the readiness for demonstration of the First Photonic Programmable Plug&Play processor device prepared for Rack-mounting and including software features to develop different applications.
The processor will include Low Losses PIC based on Silicon Photonics platform allowing a reduction of the total losses generated on chip. Additionally, there will be a development of new techniques for photonic packaging, allowing the reduction of coupling losses from the optical fibers to the PIC. Apart from that a new innovation is planned in the Transition Plan of the project and consists of designing and manufacturing of High Performance Building Block to be included in the processor for dispersion compensation applications. iPronics programmable processor has ben also used to experimentally validate a max-pooling architecture for photonic neural networks, enabling new applications in the artificial intelligence field, where the dominant hardware until today are graphic processing units (GPUs), but their computation speed is generally limited by the clock frequency as well as the memory access time."
The processor will include Low Losses PIC based on Silicon Photonics platform allowing a reduction of the total losses generated on chip. Additionally, there will be a development of new techniques for photonic packaging, allowing the reduction of coupling losses from the optical fibers to the PIC. Apart from that a new innovation is planned in the Transition Plan of the project and consists of designing and manufacturing of High Performance Building Block to be included in the processor for dispersion compensation applications. iPronics programmable processor has ben also used to experimentally validate a max-pooling architecture for photonic neural networks, enabling new applications in the artificial intelligence field, where the dominant hardware until today are graphic processing units (GPUs), but their computation speed is generally limited by the clock frequency as well as the memory access time."