Periodic Reporting for period 1 - LOLIPOP (Lithium NiObate empowered siLIcon nitride Platform for fragmentation free OPeration in the visible and the NIR)
Okres sprawozdawczy: 2022-09-01 do 2024-02-29
The silicon nitride platform is passive in nature. The hybrid solutions for emission, modulation, nonlinear processing and detection of light on this platform are still non-optimum or even totally absent if these solutions should offer at the same time, high photonic performance, wideband operation, and integration robustness. LOLIPOP is a photonic integration project that aims to fill this gap and enable the silicon nitride platform to make the next step. To this end, LOLIPOP invests on the combination of the silicon nitride with the lithium niobate on insulator (LNOI) technology, while working in parallel on the integration of semiconducting materials on the silicon nitride platform using state-of-the-art methods. The silicon nitride platform, so called TriPleX and developed by Lionix, serves in LOLIPOP as the motherboard of this new hybrid technology.
Empowered by its ambitious vision, LOLIPOP introduces a number of key innovations, summarized through the following 9 objectives:
Obj 1: Establish a process for the integration of LNOI films on the TriPleX platform, and develop hybrid TriPleX PICs that can support high-speed modulation and second-order nonlinear functions on-chip
Obj 2: Develop a process for heterogeneous integration of semiconducting layers on TriPleX wafers and growth of Ge photodiodes with wideband operation (400-1600 nm) and high bandwidth (up to 30 GHz)
Obj 3: Design active elements and develop external cavity lasers on the hybrid TriPleX platform with ultra-narrow linewidth, wide tunability and operation in the wavelength bands from 780 to 1100 nm
Obj 4: Develop CMOS electronics with low power consumption and high bandwidth (up to 30 GHz)
Obj 5: Demonstrate the use of LOLIPOP technology for Laser Doppler Vibrometers at 532 nm with ultra-high detection bandwidth (6 GHz)
Obj 6: Demonstrate the use of LOLIPOP technology for FMCW LIDAR modules at 905 nm with ultra-high chirp (10 GHz) and beam scanning mechanism on-chip
Obj 7: Demonstrate the use of LOLIPOP technology for photonic integrated convolutional neural networks with ultra-high computation speed (24 TOPS)
Obj 8: Demonstrate the use of LOLIPOP technology for integrated optical squeezed state sources
Obj 9: Work on a roadmap for the consolidation of LOLIPOP integration technology and the establishment of a low-volume production line that will offer this technology as a commercial service.
Empowered by its ambitious vision, LOLIPOP introduces a number of key innovations, summarized through the following 9 objectives:
Obj 1: Establish a process for the integration of LNOI films on the TriPleX platform, and develop hybrid TriPleX PICs that can support high-speed modulation and second-order nonlinear functions on-chip
Obj 2: Develop a process for heterogeneous integration of semiconducting layers on TriPleX wafers and growth of Ge photodiodes with wideband operation (400-1600 nm) and high bandwidth (up to 30 GHz)
Obj 3: Design active elements and develop external cavity lasers on the hybrid TriPleX platform with ultra-narrow linewidth, wide tunability and operation in the wavelength bands from 780 to 1100 nm
Obj 4: Develop CMOS electronics with low power consumption and high bandwidth (up to 30 GHz)
Obj 5: Demonstrate the use of LOLIPOP technology for Laser Doppler Vibrometers at 532 nm with ultra-high detection bandwidth (6 GHz)
Obj 6: Demonstrate the use of LOLIPOP technology for FMCW LIDAR modules at 905 nm with ultra-high chirp (10 GHz) and beam scanning mechanism on-chip
Obj 7: Demonstrate the use of LOLIPOP technology for photonic integrated convolutional neural networks with ultra-high computation speed (24 TOPS)
Obj 8: Demonstrate the use of LOLIPOP technology for integrated optical squeezed state sources
Obj 9: Work on a roadmap for the consolidation of LOLIPOP integration technology and the establishment of a low-volume production line that will offer this technology as a commercial service.
WP2: Use cases defined and module specifications outlined, with detailed component specifications established. Intermediate steps defined for module development. Extensive simulation studies conducted for optimization.
WP3: Partners independently develop building blocks, with initial tests prompting design iterations. ECL development for Modules 3+4 meets requirements. Neuromorphic chip designs show promising waveguide properties. Second-generation modules feature advancements in pocket etching and wavelength optimizations. Further optical optimization needed for fabricated chips.
WP4: Successful establishment of assembly design guidelines for LNOI PIC platform. Conducted mechanical polishing trials and defined optical losses for edge-coupling. Initiated development of Long and Short Loop runs for MTP. Established assembly design guidelines for flip-chip bonding.
WP5: Imec achieves Milestone MS08 and submits D5.1 acquiring front-end electronic components. Phix progresses towards Milestone MS09 and D5.2 establishing packaging processes. Challenges persist in coupling optical signals to/from LNOI PICs at 532 nm wavelength. Feasibility studies for packaging Ge-BPDs underway.
WP6: Optagon develops electronic units for LOLIPOP's hybrid PICs, focusing on control and activation elements. Polytec prepares vibrometer hardware and TIA-PCB for LDV modules. CSEM devises test plan for LiDAR performance assessment. Irida examines neuromorphic modules for image recognition, establishing a systematic methodology for optimization.
WP7: Partners actively communicate LOLIPOP results through social media, websites, and events. Momentum builds with first publication and provisional patent submissions, converting work into tangible assets.
WP3: Partners independently develop building blocks, with initial tests prompting design iterations. ECL development for Modules 3+4 meets requirements. Neuromorphic chip designs show promising waveguide properties. Second-generation modules feature advancements in pocket etching and wavelength optimizations. Further optical optimization needed for fabricated chips.
WP4: Successful establishment of assembly design guidelines for LNOI PIC platform. Conducted mechanical polishing trials and defined optical losses for edge-coupling. Initiated development of Long and Short Loop runs for MTP. Established assembly design guidelines for flip-chip bonding.
WP5: Imec achieves Milestone MS08 and submits D5.1 acquiring front-end electronic components. Phix progresses towards Milestone MS09 and D5.2 establishing packaging processes. Challenges persist in coupling optical signals to/from LNOI PICs at 532 nm wavelength. Feasibility studies for packaging Ge-BPDs underway.
WP6: Optagon develops electronic units for LOLIPOP's hybrid PICs, focusing on control and activation elements. Polytec prepares vibrometer hardware and TIA-PCB for LDV modules. CSEM devises test plan for LiDAR performance assessment. Irida examines neuromorphic modules for image recognition, establishing a systematic methodology for optimization.
WP7: Partners actively communicate LOLIPOP results through social media, websites, and events. Momentum builds with first publication and provisional patent submissions, converting work into tangible assets.
WP2: Initial definition of LOLIPOP technology's application space, system requirements, module designs, and component specifications. Development of design rules, packaging strategies, and system level simulation layouts. Power budget analysis for intermediate modules completed.
WP3: Completion and transfer of all TriPleX designs. Development of cost-effective pocket etching in TriPleX. Growth and characterization of first Ge islands. Fabrication of majority of PICs for modules. Design and development of all LNOI subcircuits and active elements.
WP4: Establishment of assembly design guidelines for LNOI PIC platform. Successful mechanical polishing trials and optical losses definition for edge-coupling. Development of MTP at TYNDALL. Pickup and printing of initial samples from test structures. Establishment of assembly design guidelines for flip-chip bonding.
WP5: Definition and revision of electronic requirements. Selection of driver and TIA ICs. Proposal of front-end PCB solution. Design, fabrication, and characterization of custom PCB for LNOI modulators. Successful packaging of various TriPleX components. Successful edge-coupling between multiple fiber array – TriPleX PICs. Establishment of packaging process for Ge-BPmmD.
WP6: Development of multi-channel laser diode drivers, heating electrode drivers, and TEC solution. Testing of control electronics unit. Progress on PZT drivers. Preparation of digital part of control electronics unit for Module-1. Design of TIA electronics. Methodology and scenarios for module evaluation defined and partially tested. Vibrometer hardware set up. Testing scenarios and demonstration scenarios designed for Neuromorphic Chips.
WP7: Interview with customers, partners, and networks conducted. Initial Data Management Plan prepared. Implementation of Exploitation plan with Dissemination & Communication activities. Setup and monitoring of project website and social media accounts. Initial Dissemination & Counication activities performed. First scientific paper and provisional patent submitted. First market interaction with 1064 nm ECL.
WP3: Completion and transfer of all TriPleX designs. Development of cost-effective pocket etching in TriPleX. Growth and characterization of first Ge islands. Fabrication of majority of PICs for modules. Design and development of all LNOI subcircuits and active elements.
WP4: Establishment of assembly design guidelines for LNOI PIC platform. Successful mechanical polishing trials and optical losses definition for edge-coupling. Development of MTP at TYNDALL. Pickup and printing of initial samples from test structures. Establishment of assembly design guidelines for flip-chip bonding.
WP5: Definition and revision of electronic requirements. Selection of driver and TIA ICs. Proposal of front-end PCB solution. Design, fabrication, and characterization of custom PCB for LNOI modulators. Successful packaging of various TriPleX components. Successful edge-coupling between multiple fiber array – TriPleX PICs. Establishment of packaging process for Ge-BPmmD.
WP6: Development of multi-channel laser diode drivers, heating electrode drivers, and TEC solution. Testing of control electronics unit. Progress on PZT drivers. Preparation of digital part of control electronics unit for Module-1. Design of TIA electronics. Methodology and scenarios for module evaluation defined and partially tested. Vibrometer hardware set up. Testing scenarios and demonstration scenarios designed for Neuromorphic Chips.
WP7: Interview with customers, partners, and networks conducted. Initial Data Management Plan prepared. Implementation of Exploitation plan with Dissemination & Communication activities. Setup and monitoring of project website and social media accounts. Initial Dissemination & Counication activities performed. First scientific paper and provisional patent submitted. First market interaction with 1064 nm ECL.