Periodic Reporting for period 1 - MultiSpin.AI (n-ary spintronics-based edge computing co-processor for artificial intelligence)
Okres sprawozdawczy: 2024-02-01 do 2025-01-31
Artificial Intelligence (AI) has demonstrated its transformative potential with applications in language models, medical diagnostics, industrial automation, and more. It has generated an astounding €2.7 trillion in business value in 2021 alone, and forecasts predict AI will generate €12T in value by 2030. However, as the demand for AI increases, existing computing architectures, constrained by their intrinsic limitations, are struggling to keep pace. Global data processing reached 97ZB in 2022, and this volume is doubling every two-three years, overwhelming the capabilities of even next-generation technologies like 5G and 6G.
MultiSpin.AI is set to innovate the world of AI through development of an n-ary spintronics-based edge computing co-processor. This technology aims to overcome the limitations of current computing hardware and enable AI to address some of the world’s most pressing global challenges, from healthcare to climate change, transportation, and food security.
Challenge: Overcoming the Limitations of Existing AI Hardware
The progress of current computing technology is impeded due to major obstacles:
1. Von Neumann Bottleneck: Traditional computing architectures separate processing and memory units, creating a data transfer bottleneck that slows down AI computations.
2. End of Moore’s and Dennard’s Laws: With transistor sizes shrinking to 2nm, the semiconductor industry is approaching physical limits, leaving little room for further improvements in computing power.
3. Energy Consumption: Information and communication technologies (ICT) are on track to consume up to 21% of global energy by 2030, posing a serious threat to sustainability goals.
Solution: New Era of Spintronics-based AI Co-processors
MultiSpin.AI uses spintronics-based technology to develop an edge computing co-processor designed for AI application. This co-processor will enhance energy efficiency, computational speed, and accuracy, overcoming the limitations of current hardware architectures. It will also enable AI to process data locally at the edge—closer to the source—rather than relying on centralized cloud computing, reducing latency, bandwidth, and energy consumption.
Project Objectives: Pushing the Boundaries of AI and Spintronics
The goal of MultiSpin.AI is to design, fabricate, and test AI inference with innovative n-ary multistate magnetic tunnel junctions. Thus, instead of existing binary magnetic tunnel junctions, these structures can switch between multiple magnetic states, providing unprecedented speed and energy efficiency for AI computations.
The strategy of MultiSpin.AI for achieving this goal is to operate in three levels with increasing complexity: (a) single layer multi -level structures (SLMMS) (b) multi-level magnetic tunnel junctions (M2TJ) where one of the magnetic layers of the junctions is a SLMMS, and (c) a crossbar of M2TJ that will be integrated into the proof-of-concept prototype. While we aspire to demonstrate 16 discrete magnetic states with the SLMMS, in the crossbar we will aim for M2TJs with 4 resistance states. Based on this strategy we will be able to demonstrate the potential of this technology not only based on the prototype but also on the expected performance of crossbars consisting of M2TJs with more than 4 resistance states.
The image attached to the report shows a bottom magnetic layer consisting of two crossing ellipses and a top magnetic layer consisting of a single ellipse. The multi resistance states of the M2TJ are related to the multiple magnetic states supported by the bottom magnetic layer.
MultiSpin.AI is set to innovate the world of AI through development of an n-ary spintronics-based edge computing co-processor. This technology aims to overcome the limitations of current computing hardware and enable AI to address some of the world’s most pressing global challenges, from healthcare to climate change, transportation, and food security.
Challenge: Overcoming the Limitations of Existing AI Hardware
The progress of current computing technology is impeded due to major obstacles:
1. Von Neumann Bottleneck: Traditional computing architectures separate processing and memory units, creating a data transfer bottleneck that slows down AI computations.
2. End of Moore’s and Dennard’s Laws: With transistor sizes shrinking to 2nm, the semiconductor industry is approaching physical limits, leaving little room for further improvements in computing power.
3. Energy Consumption: Information and communication technologies (ICT) are on track to consume up to 21% of global energy by 2030, posing a serious threat to sustainability goals.
Solution: New Era of Spintronics-based AI Co-processors
MultiSpin.AI uses spintronics-based technology to develop an edge computing co-processor designed for AI application. This co-processor will enhance energy efficiency, computational speed, and accuracy, overcoming the limitations of current hardware architectures. It will also enable AI to process data locally at the edge—closer to the source—rather than relying on centralized cloud computing, reducing latency, bandwidth, and energy consumption.
Project Objectives: Pushing the Boundaries of AI and Spintronics
The goal of MultiSpin.AI is to design, fabricate, and test AI inference with innovative n-ary multistate magnetic tunnel junctions. Thus, instead of existing binary magnetic tunnel junctions, these structures can switch between multiple magnetic states, providing unprecedented speed and energy efficiency for AI computations.
The strategy of MultiSpin.AI for achieving this goal is to operate in three levels with increasing complexity: (a) single layer multi -level structures (SLMMS) (b) multi-level magnetic tunnel junctions (M2TJ) where one of the magnetic layers of the junctions is a SLMMS, and (c) a crossbar of M2TJ that will be integrated into the proof-of-concept prototype. While we aspire to demonstrate 16 discrete magnetic states with the SLMMS, in the crossbar we will aim for M2TJs with 4 resistance states. Based on this strategy we will be able to demonstrate the potential of this technology not only based on the prototype but also on the expected performance of crossbars consisting of M2TJs with more than 4 resistance states.
The image attached to the report shows a bottom magnetic layer consisting of two crossing ellipses and a top magnetic layer consisting of a single ellipse. The multi resistance states of the M2TJ are related to the multiple magnetic states supported by the bottom magnetic layer.
During the first year the work has been performed in several parallel efforts:
1. We designed & fabricated novel magnetic structures that can support multiple magnetic states, namely single layer multi-level structures (SLMMS) and multi-level magnetic tunnel junctions (M2TJ). The SLMMS are devices in the form of single, two and three crossing ellipses exhibiting, uniaxial, bi-axial and tr-axial anisotropy, respectively. The M2TJs are tunnel junctions where the bottom ferromagnetic layer is in the form of 2 crossing ellipses. (WP2)
2. We performed characterization of the electric and magnetic properties of the SLMMS and M2TJ devices. In addition, we have tested the current-induced switching of SLMMS. (WP3)
3. We developed algorithms to exploit n-ary cells instead of binary cells in crossbar memories for performing MAC (Multiply-and-Accumulate) operations. Our approach effectively addresses the challenges associated with this transition by enabling the MAC operation using the proposed hardware. Additionally, our algorithm allows for the simulation of any crossbar size and provides insights into the impact of cell-to-cell variability and electrical measurement noise on system performance. (WP4)
4. We performed simulations of SLMMS for optimization of design and materials. (WP2)
5. We also simulated the expected spin-orbit torques in for different structures in SLMMS and explored the effect of existing magnetic gradients on the spin orbit torques as measured by second harmonics. (WP3)
6. We started the POC planning – The discussions on the matrix device readout scheme started with the definition of the device biasing requirements, multiplexing and individual memory element addressing. These will continue, so to integrate the relevant performing indicators for an electronic device. Furthermore we developed high level architecture of the PoC board, combining limited-scale spintronic crossbar with discrete peripherals. (WP5)
Main achievements:
1. Demonstration the ability to stabilize 12 discrete magnetic states in SLLMs.
2. Demonstration of current induced switching of SLMMS by micro-second pulses in preparation for switching with nano-second pulses
3. Developed algorithms for crossbar memories using n-ary instead of binary cells to perform MAC operations, overcoming challenges and simulating impact of cell-to-cell variability and noise on any crossbar size.
1. We designed & fabricated novel magnetic structures that can support multiple magnetic states, namely single layer multi-level structures (SLMMS) and multi-level magnetic tunnel junctions (M2TJ). The SLMMS are devices in the form of single, two and three crossing ellipses exhibiting, uniaxial, bi-axial and tr-axial anisotropy, respectively. The M2TJs are tunnel junctions where the bottom ferromagnetic layer is in the form of 2 crossing ellipses. (WP2)
2. We performed characterization of the electric and magnetic properties of the SLMMS and M2TJ devices. In addition, we have tested the current-induced switching of SLMMS. (WP3)
3. We developed algorithms to exploit n-ary cells instead of binary cells in crossbar memories for performing MAC (Multiply-and-Accumulate) operations. Our approach effectively addresses the challenges associated with this transition by enabling the MAC operation using the proposed hardware. Additionally, our algorithm allows for the simulation of any crossbar size and provides insights into the impact of cell-to-cell variability and electrical measurement noise on system performance. (WP4)
4. We performed simulations of SLMMS for optimization of design and materials. (WP2)
5. We also simulated the expected spin-orbit torques in for different structures in SLMMS and explored the effect of existing magnetic gradients on the spin orbit torques as measured by second harmonics. (WP3)
6. We started the POC planning – The discussions on the matrix device readout scheme started with the definition of the device biasing requirements, multiplexing and individual memory element addressing. These will continue, so to integrate the relevant performing indicators for an electronic device. Furthermore we developed high level architecture of the PoC board, combining limited-scale spintronic crossbar with discrete peripherals. (WP5)
Main achievements:
1. Demonstration the ability to stabilize 12 discrete magnetic states in SLLMs.
2. Demonstration of current induced switching of SLMMS by micro-second pulses in preparation for switching with nano-second pulses
3. Developed algorithms for crossbar memories using n-ary instead of binary cells to perform MAC operations, overcoming challenges and simulating impact of cell-to-cell variability and noise on any crossbar size.
WP5 is developing an architecture for the proof-of-concept (PoC) featuring a 4×4 4-level M2TJs-based crossbar along with the necessary peripherals, to demonstrate the feasibility of spintronics-based analog neuromorphic AI acceleration using 2-bit (4 states) M2TJs. Once completed and tested it will highlight the potential of the technology in delivering energy-efficient AI processing. To further validate its real-world applicability, relevant AI use-cases are being evaluated to provide a clear demonstration of MultiSpin.AI's capabilities. This ongoing assessment will help refine the technology and showcase its advantages in practical AI scenarios, paving the way for further scaling, commercialization, and industrial adoption.