FD-SOI Pilot Line for Applications with embedded non-volatile Memories, RF, 3D integration and PMIC, to ensure European Sovereignty

CORDIS proporciona enlaces a los documentos públicos y las publicaciones de los proyectos de los programas marco HORIZONTE.

Los enlaces a los documentos y las publicaciones de los proyectos del Séptimo Programa Marco, así como los enlaces a algunos tipos de resultados específicos, como conjuntos de datos y «software», se obtienen dinámicamente de OpenAIRE .

Resultado final

D1.4.3: Non-volatile memory and 3D integration Process Design-Kit add-on for MAD305 MPW test vehicle

Delivery of the Process Design-Kit add-on to set-up the MAD305 maskset

D11.1.2 : Process-level E-score tool

Deliver a standalone E-Score tool for evaluation of selected impact factors for individual process steps for different fab processing areas such as etch, deposition and lithography.

D1.4.5: First 10nm FD-SOI Process Design-Kit for benchmarking

Delivery of the first Process Design-Kit dedicated to the benchmarking of the 10nm FD-SOI technology

D10.2.1: Test report on FM-IR-UWB RADAR sub-blocks

This deliverable reports the radar system dimensioning (analogue and digital), the design and the test of the following sub-parts: ADPLL, Wideband modulator, IF receiver

D10.4.1: Mixed-signal Ising computing chip based on phase-domain processing using oscillators

We will prototype an Ising-inspired optimization solver based on electrically-coupled Kuramoto oscillators in CMOS technology, computing through their global phase dynamics. We will use the demonstrator to solve graph partitioning or Boolean satisfiability problems, which are known to be NP-complete, targeting a power consumption per node of less than 100µW.

D11.1.1: LCA methods

Definition of the relevant LCA methodology

D13.2: Initial Dissemination and Communication Plan

The Communication and Dissemination plan will include dissemination goals, information to be disseminated, targeted stakeholders, timelines and KPIs.

D13.1: Press Release – Project Announcement

Public Press Release to announce the start of the project.

D14.4: Organization of a European FD-SOI School

This school will offer lectures and trainings for FD-SOI designers. This EFDS will be organized as a pilot school.

D14.5: Organization of FAMES School (2025)

This school will offer lectures and trainings about FAMES technologies (NVM, RF, 3D, PMIC)

D14.3: Setup of a training related to: “from CMOS to the fundamentals of FD-SOI and memories” and creation of a pool of trainers

Training program describing the audience, skills, prerequisites, training content and list of trainers

Publicaciones

Ising-inspired invertible adders using coupled phase-locked CMOS ring oscillators

Autores: Ali Bazzi, Hugo Levices, Philippe Talatchian, Franck Badets, Louis Hutin
Publicado en: Physical Review Applied, Edición 24, 2025, ISSN 2331-7019
Editor: American Physical Society (APS)
DOI: 10.1103/8XC2-VKK3

300 Mm sSOI engineering with ultra thin buried oxide

Autores: D. Barge; M. Gallard; J.-M. Hartmann; F. Fournel; V. Loup; F. Mazen; E. Nolot; P. Hauchecorne; J. Sturm; V.H. Le; I. Huyet; D. Delprat; F. Boedt; F. Servant
Publicado en: Solid-State Electronics, 2026, ISSN 0000-0000
Editor: EuroSOI-ULIS 2025’ published in Solid State Electronics.
DOI: 10.1016/J.SSE.2025.109307

Intrinsic annealing in a hybrid memristor-magnetic tunnel junction Ising machine

Autores: Mohammed Akib Iftakher, Hugo Levices, Kamel-Eddine Harabi, Adrien Renaudineau, Mathieu-Coumba Faye, Corentin Bouchard, Florian Disdier, Bernard Viala, Elisa Vianello, Philippe Talatchian, Kevin Garello, Damien Querlioz, Louis Hutin
Publicado en: Nature Communications, Edición 17, 2026, ISSN 2041-1723
Editor: Springer Science and Business Media LLC
DOI: 10.1038/S41467-026-71844-8

Toward full relaxation of sSOI substrates for PFET device fabrication

Autores: N-P. Tran; F. Milesi; V-H. Le; L-D. Mohgouk Zouknak; P. Dezest; Ph. Rodriguez; L. Brunet; B. Duriez; M-C. Cyrille; C. Fenouillet-Beranger
Publicado en: Solid-State Electronics, Edición Volume 229, November 2025, 109196, 2025, ISSN 0000-0000
Editor: 2025 Elsevier Ltd for EuroSOI-ULIS 2025’ published in Solid State Electronics.
DOI: 10.1016/J.SSE.2025.109196

Simulation of Interference‐Enhanced Raman Amplification for Advanced Microelectronic Applications

Autores: D. Monteil, Y. Mazel, F. Deprat, E. Prevost, R. Duru, D. Le Cunff, E. Nolot, V. H. Le, P. Quéméré, M. Mermoux
Publicado en: physica status solidi (a), Edición 223, 2026, ISSN 1862-6300
Editor: Wiley
DOI: 10.1002/PSSA.202501030

Bayesian continual learning and forgetting in neural networks

Autores: Djohan Bonnet, Kellian Cottart, Tifenn Hirtzlin, Tarcisius Januel, Thomas Dalgaty, Elisa Vianello, Damien Querlioz
Publicado en: Nature Communications, Edición 16, 2025, ISSN 2041-1723
Editor: Springer Science and Business Media LLC
DOI: 10.1038/S41467-025-64601-W

Selective Epitaxial Growth of SiGe(:B) for Advanced p-Type Fd-SOI

Autores: Justine Lespiaux, Joël Kanyandekwe, Tanguy Marion, Lazhar Saidi, Valérie Lapras, Alice Bond, Fabien Bringuier, Jérôme Richy, Alan Thouvard, Tim Biet
Publicado en: ECS Transactions, Edición Volume 114, Number 2, 2024, ISSN 1938-5862
Editor: IOP Publishing
DOI: 10.1149/11402.0271ECST

Modeling of RRAM based PUF: a case study

Autores: Kamil Ber, Piotr Wiśniewski
Publicado en: Solid-State Electronics, Edición 231, 2026, ISSN 0038-1101
Editor: Elsevier BV
DOI: 10.1016/J.SSE.2025.109267

Al 2 O 3 Capping and ZrO 2 Seed Layer Optimization in Hafnia‐Based Top‐Electrodeless Annealed Ferroelectric Capacitors for Stable Switching Postwake‐Up

Autores: Patrik Eskelinen, Oscar Kaatranen, Kimmo Rutanen, Jacek Flak, Olli‐Pekka Kilpi, Karl‐Magnus Persson
Publicado en: physica status solidi (RRL) – Rapid Research Letters, Edición 20, 2026, ISSN 1862-6254
Editor: Wiley
DOI: 10.1002/PSSR.202600002

Influence of Dopant and Si:B Cap on Ni(Pt)-Based Silicidation of SiGe:B for Next Generation PMOS FDSOI Devices

Autores: Helen Grampeix; Théo Cabaret; Justine Lespiaux; Patrice Gergaud; Nicolas Gauthier; Philippe Rodriguez
Publicado en: 2025 22nd International Workshop on Junction Technology (IWJT), 2025, ISSN 0000-0000
Editor: IEEE
DOI: 10.23919/IWJT66253.2025.11072894

On the Enhanced p‐Type Performance of Back‐Gated WS2 Devices

Autores: Carlos Marquez, Farzan Gity, Jose C. Galdon, Alberto Martinez, Norberto Salazar, Lida Ansari, Hazel Neill, Luca Donetti, Francisco Lorenzo, Manuel Caño‐Garcia, Ruben Ortega, Carlos Navarro, Carlos Sampedro, Paul K. Hurley, Francisco Gamiz
Publicado en: Advanced Electronic Materials, Edición 11, 2025, ISSN 2199-160X
Editor: Wiley
DOI: 10.1002/AELM.202500079

Diffusion Analysis and Impact of RTA on Strained Phosphorous-Doped Si for Advanced SOI Nodes

Autores: Theo Cabaret, Eva Dos Reis, Valerie Lapras, Nicolas Gauthier, Joel Kanyandekwe
Publicado en: IEEE Journal of the Electron Devices Society, Edición 13, 2025, ISSN 2168-6734
Editor: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/JEDS.2025.3642939

Dual-Mode Wideband Receiver Operating with Frequency Modulated Impulse Radar Waveform

Autores: Mykhailo Zarudniev; Laurent Ouvry; Gilles Masson; Arthur Paviot; Cedric Dehos; Pierre Courouve; David Lachartre
Publicado en: 2025 IEEE Radar Conference (RadarConf25), 2025, ISSN 2375-5318
Editor: IEEE
DOI: 10.1109/RADARCONF2559087.2025.11205075

Selective Epitaxy of Tensile, Highly Doped SiP for Planar NMOS FD-SOI Devices

Autores: Joel Kanyandekwe, Jean-Michel Hartmann, Justine Lespiaux, Tanguy Marion, Lazhar Saidi, Valérie Lapras, Alice Bond, Fabien Bringuier, Jérôme Richy, Nicolas Gauthier, Alan Thouvard, Tim Biet, Ludovic Couture, Adrien Blot-Saby, Agathe Andre, Jérémy Marchand, Christophe Licitra, Remi Coquand, Alexis Royer, Tristan Dewolf, Haidar Al Dujaili, Andrea Lassenberger, Olivier Glorieux
Publicado en: ECS Transactions, Edición 114, 2024, ISSN 1938-5862
Editor: The Electrochemical Society
DOI: 10.1149/11402.0253ECST

300 Mm sSOI engineering with ultra thin buried oxide

Autores: D. Barge, M. Gallard, J.-M. Hartmann, F. Fournel, V. Loup, F. Mazen, E. Nolot, P. Hauchecorne, J. Sturm, V.H. Le, I. Huyet, D. Delprat, F. Boedt, F. Servant
Publicado en: Solid-State Electronics, Edición 232, 2025, ISSN 0038-1101
Editor: Elsevier BV
DOI: 10.1016/J.SSE.2025.109307

Wafer-Scale Demonstration of BEOL-Compatible Ambipolar MoS2 Devices Enabled by Plasma-Enhanced Atomic Layer Deposition

Autores: Alberto Martínez; Carlos Márquez; Francisco Lorenzo; Francisco Gutiérrez; Manuel Caño-García; Jorge Ávila; José Carlos Galdón Gil; Ruben Ortega Lopez; Carlos Navarro; Luca Donetti; Francisco Gámiz
Publicado en: ACS Applied Materials & Interfaces, 2025, ISSN 0000-0000
Editor: ACS Publications
DOI: 10.1021/ACSAMI.5C12014

Europe’s pilot line on fully depleted silicon-on-insulator technology (FAMES)

Autores: Jean-René Lèquepeys, Dominique Noguet, Bruno Paing, Xavier Lemoine, Christophe Wyon, Marie-Claire Cyrille, Claire Fenouillet-Béranger, Eric Dupont-Nivet, Chrystel Deguet, Susana Bonnetier
Publicado en: Nature Reviews Electrical Engineering, Edición 2, 2025, ISSN 2948-1201
Editor: Springer Science and Business Media LLC
DOI: 10.1038/S44287-025-00144-Y

Nanoscale SOI strain engineering: STRASS-enabled local stress optimization

Autores: L.D. Mohgouk Zouknak; V-H. Le; N-P. Tran; F. Milesi; J.-M. Hartmann; S. Jarjayes; J. Lespiaux; A. Jannaud; F. Aussenac; N. Bernier; Ph. Rodriguez; L. Brunet; B. Duriez; M.C. Cyrille; C. Fenouillet-Beranger
Publicado en: Solid-State Electronics, 2025, ISSN 0000-0000
Editor: EuroSOI-ULIS 2025’ published in Solid State Electronics.
DOI: 10.1016/J.SSE.2025.109215

Investigation of compliance current effect on resistive switching properties in Ag/SiOx/Cr RRAM devices

Autores: Piotr Wiśniewski, Piotr Jeżak, Aleksander Małkowski, Alicja Kądziela, Jakub Krzemiński, Robert Mroczyński
Publicado en: Solid-State Electronics, Edición 231, 2026, ISSN 0038-1101
Editor: Elsevier BV
DOI: 10.1016/J.SSE.2025.109288

Ferroelectric HfO 2 /ZrO 2 Superlattice Capacitors With High Center to Edge Wafer‐Scale Uniformity

Autores: Oscar Kaatranen, Patrik Eskelinen, Sampo Inkinen, Olli‐Pekka Kilpi, Karl‐Magnus Persson
Publicado en: Advanced Electronic Materials, Edición 12, 2026, ISSN 2199-160X
Editor: Wiley
DOI: 10.1002/AELM.202500773

Exploring the relationship between doping and Ti-silicidation for advanced FDSOI applications

Autores: Marie Merlin, Théo Cabaret, Helen Grampeix, Nicolas Gauthier, Mario Ghostine, Joel Kanyandekwe, Philippe Rodriguez, Patrice Gergaud
Publicado en: Microelectronic Engineering, Edición 306, 2026, ISSN 0167-9317
Editor: Elsevier BV
DOI: 10.1016/J.MEE.2026.112482

Wafer‐Scale Demonstration of Polycrystalline MoS2 Growth on 200 mm Glass and SiO2/Si Substrates by Plasma‐Enhanced Atomic Layer Deposition

Autores: Julia Jagosz, Leander Willeke, Nils Gerke, Malte J. M. J. Becher, Paul Plate, Aleksander Kostka, Detlef Rogalla, Andreas Ostendorf, Claudia Bock
Publicado en: Advanced Materials Technologies, Edición 9, 2025, ISSN 2365-709X
Editor: Wiley
DOI: 10.1002/ADMT.202400492

Pursuing the FD-SOI roadmap down to 10 nm and 7 nm nodes for high energy efficient, low power and RF/mmWave applications

Autores: C. Fenouillet-Beranger; O. Rozeau; R. Chouk; O. Cueto; A-S. Royet; M. Charbonneau; B. Mohamad; L. Brévard; Z. Chalupa; A. Bond; F. Baudin; L. Brunet; P. Rodriguez; R. Gassilloud; T. Mota-Frutuoso; P. Pimenta-Barros; S. Beaurepaire; V. Lapras; J. Kanyandekwe; E. Petitprez; P. Brianceau; R. Segaud; null S.Verrun; D. Barge; P. Chausse; O. Billoint; W. Vandendaele; K. Romanjek; V. Loup; J-M. Hartmann; A. Magalhaes-Lucas; G. Garnier; A. Souhaité; G. Cibrario; B. Duriez; T. Poiroux; M-C. Cyrille; D. Noguet
Publicado en: Solid-State Electronics, 2026, ISSN 0000-0000
Editor: Solid-State Electronics SSRN
DOI: 10.1016/J.SSE.2025.109264

Fast CV MSM Technique for Comprehensive Analysis of Bulk Trapping in Low-K Carbon-Doped Dielectrics

Autores: T. Mota Frutuoso, W. Vandendaele, A. Bond, F. Bringuier, V. Lapras, M. C. Cyrille, C. Fenouillet-Beranger, B. Duriez. X. Garros
Publicado en: 2025 IEEE International Reliability Physics Symposium (IRPS), 2025
Editor: IEEE
DOI: 10.1109/IRPS48204.2025.10983765

Ultra-Thin-Body and Buried Oxide FD-SOI next generation nodes and eNVM technologies for advanced IC design

Autores: Claire Fenouillet-Beranger, Laurent Fesquet, Rihab Chouk, Gabriel Pares, Baudoin Martineau, Marie-Claire Cyrille, Thierry Poiroux, Olivier Billoint, Dominique Noguet
Publicado en: 2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2025
Editor: IEEE
DOI: 10.1109/DDECS63720.2025.11006678

Breakthrough Processes for Si CMOS Devices with BEOL Compatibility for 3D Sequential Integrated more than Moore Analog Applications

Autores: D. Bosch, A. Viey, T. Mota Frutuoso, P. Lheritier, C. Licitra, N. Zerhouni, A. Albouy, L. Brunet, A. Magalhaes-Lucas, L. M. B. da Silva, H. Boutry, M. Husien Fahmy Taha Abdelrahman, F. Cristiano, R. G
Publicado en: 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2025
Editor: IEEE
DOI: 10.1109/VLSITECHNOLOGYANDCIR46783.2024.10631398

A Low-Power Bayesian Head Using SOT-MRAM Arrays for Uncertainty-Aware Binary Neural Networks

Autores: Joao Henrique Quintino Palhares, Bruno Lovison Franco, Louis Hutin, Jonathan Miquel, Kamel-Eddine Harabi, Aymen Romdhane, Kevin Garello
Publicado en: 2026 Design, Automation &amp; Test in Europe Conference (DATE), 2026
Editor: IEEE
DOI: 10.23919/DATE69613.2026.11539540

Impact of Rapid Thermal Annealing on Tensily-Strained Phosphorous-Doped Si for Advanced FD-SOI Nodes

Autores: Theo Cabaret, Eva Dos Reis, Valerie Lapras, Nicolas Gauthier, Joel Kanyandekwe
Publicado en: 2025 22nd International Workshop on Junction Technology (IWJT), 2025
Editor: IEEE
DOI: 10.23919/IWJT66253.2025.11072902

TiSiN sputtered films as Copper diffusion barriers

Autores: Francesca Corbella; Jean-Baptiste Dory; Nicolas Gauthier; Eleonora Garoni
Publicado en: 2025
Editor: 2025 IEEE International Interconnect Technology Conference (IITC)
DOI: 10.1109/IITC66087.2025.11075410

In-depth energy analysis of a hybrid sMTJ/RRAM Ising machine

Autores: H. Levices, M-A. Iftakher, K-E. Harabi, M-C. Faye, P. Talatchian, K. Garello, D. Querlioz, L. Hutin
Publicado en: 2026 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), 2026
Editor: IEEE
DOI: 10.1109/VLSITSA69131.2026.11527654

Hybrid bonding with ultra-low temperature annealing: morphological and electrical validations

Autores: Margot Faure, Agathe Lerat, Pablo Renaud, Floriane Baudin, Maria-Luisa Calvo-Muñoz, Hadi Hijazi, Frank Fournel, Christophe Dubarry
Publicado en: 2026 IEEE 76th Electronic Components and Technology Conference (ECTC), 2026
Editor: IEEE
DOI: 10.1109/ECTC51846.2026.00022

FD-SOI rather than Bulk - Experimental investigation of laser induced fault mechanisms in FD-SOI

Autores: Loïc Mangin, Krishna Pradeep, Romain Wacquez, Laurent Maingault, Philippe Flatresse, Adrià Calvo Bellocq, Rainer Lutz
Publicado en: 2026 IEEE 32nd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2026
Editor: IEEE
DOI: 10.1109/IOLTS69666.2026.11633739

In-line Raman spectroscopy for semiconductors strain engineering and control : Topic/Category AM: Advanced Metrology

Autores: Zsolt Szekrényes, Van-Hoan Le, Pierre Bellanger, Leila Badeeb, Bálint Éles, Anikó Ildikó Faragó, Emmanuel Nolot, David Barge, Manon Gallard, Jean-Michel Hartmann, Pauline Hauchecorne, Virginie Loup, Julian Sturm, Amal Sediri, Róbert Bolla, Réka Petrovszki, Balázs Gombkötő, Bálint Somogyi, György Nádudvari, Anita Pongrácz, Maximilien Dallery, Nicolas Laurent
Publicado en: 2025 36th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2025
Editor: IEEE
DOI: 10.1109/ASMC64512.2025.11010779

Strain Engineering for Next-Generation FDSOI MOSFET, Probing CESL Relaxation with Xe, Ar, and Ge Ion Implantation

Autores: L. D. Mohgouk Zouknak, B. Mohamad, K. Romanjek, L. Lachal, Z. Chalupa, M. Charbonneau, W. Vandendaele, V. Mandrillon, F. Mazen, A. Anotta, N. Gauthier, D. Mariolle, L. Brévard, L. Brunet, Ph. Rodriguez, B. Duriez, M. C. Cyrille, C. Fenouillet-Beranger
Publicado en: 2026 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), 2026
Editor: IEEE
DOI: 10.1109/VLSITSA69131.2026.11527593

Process challenges of the STRASS technique to increase the electron mobility in advanced FDSOI nMOSFETs

Autores: Milesi, F., Rodriguez, P., Zouknakl, L.D.M. et al.
Publicado en: MRS Advances, Edición 10, 174-178, 2025
Editor: MRS Advances
DOI: 10.1557/S43580-025-01148-4

Reaching the BTI 10yrs Lifetime for 2.5V BEOL Compatible (<420° C) High Voltage Si-CMOS

Autores: W. Vandendaele, D. Bosch, M. Ribotta, T. Mota Frutuoso, R. Gasilloud, A.G. Viey, X. Garros, P. Batude
Publicado en: 2026 IEEE International Reliability Physics Symposium (IRPS), 2026
Editor: IEEE
DOI: 10.1109/IRPS61424.2026.11499319

Engineering 3D HZO Ferroelectric Capacitors to Scale Down 22nm Embedded FeRAM

Autores: S. Martin, C. Jahan, R. Blanc, G. Persson, F. Grimaud, M. Louro, L. Hosier, N. Giovannelli, T. Monniez, G. Boniface, O. Glorieux, C. Boixaderas, A. Roman, M. Oujanba, M. Bedjaoui, J. Mercier, S. Minoret, C. Euvrard, J. Sturm, C. Candegabe, S. Kerdiles, C. Comboroure, E. Guyez, S. Pocas, D. Ly, S. Martinie, Y. Beilliard, G. Pares, F. Bernard-Granger, J. Coignus, N. Bernier, O. Billoint, F. Andrieu, L. Grenouillet
Publicado en: 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2026
Editor: IEEE
DOI: 10.1109/VLSITECHNOLOGYANDCIR65830.2026.11577270

Modeling the Impact of High-$\kappa$ Thickness Scaling (Down to 1.1 nm) on Gate Leakage and PBTI in Advanced FDSOI Devices

Autores: Elhadji Alhousseyni Diallo, Tadeu Mota Frutuoso, William Vandendaele, Laurent Brévard, Claire Fenouillet-Beranger, Marie-Claire Cyrille, Xavier Garros
Publicado en: 2026 IEEE International Reliability Physics Symposium (IRPS), 2026
Editor: IEEE
DOI: 10.1109/IRPS61424.2026.11499342

Evaluation of Sidewalls Properties in HZO-Based 3D Ferroelectric Capacitors

Autores: Nicolò Giovannelli, Jean Coignus, Simon Martin, Julien Borrel, Carine Jahan, Antoine Salvi, Fabien Grimaud, Melanie Louro, Romuald Blanc, Corinne Comboroure, Christelle Boixaderas, Mehdi Oujanba, Stéphane Minoret, Julian Sturm, Damien Deleruyelle, François Andrieu, Laurent Grenouillet
Publicado en: 2026 IEEE International Memory Workshop (IMW), 2026
Editor: IEEE
DOI: 10.1109/IMW68301.2026.11532893

Tether-Free Micro-Transfer-Printing of Si-based Micro-Inductors: Demonstration of on-Glass and in-Silicon Integration for PowerSoC applications

Autores: Amit Tanwar, Muhammet Genc, Liang Ye, Rayan Bajwa, Somnath Pal, Iurii Efimenkov, Ranajit Sai, Cian O’Mathuna, Brian Corbett, Sambuddha Khan
Publicado en: 2026 IEEE 76th Electronic Components and Technology Conference (ECTC), 2026
Editor: IEEE
DOI: 10.1109/ECTC51846.2026.00202

Calibration Insights of Phosphorus Diffusion Model for NMOS FDSOI : Pathway to Advanced Technology Nodes

Autores: A-S. Royet; R. Chouk; O. Cueto; J. Kanyandekwe; V. Lapras; M-A. Jaud
Publicado en: 2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2024
Editor: IEEE
DOI: 10.1109/SISPAD62626.2024.10733008

Die-To-Wafer Hybrid Bonding Technology down to 1 μm pitch for Multi-Die Stacking Integration

Autores: Melissa Najem, Agathe Lerat, Carine Ladner, Loic Sanchez, Julien Diaz, Renan Bouis, Jérôme Dechamp, Antonio Roman, Myriam Assous, Damien Saint-Patrice, Lilian Masarotto, Stéphane Nicolas
Publicado en: 2026 IEEE 76th Electronic Components and Technology Conference (ECTC), 2026
Editor: IEEE
DOI: 10.1109/ECTC51846.2026.00218

Enhanced Ferroelectricity in $\text{Hf}_{0.5} \text{Zr}_{0.5} \mathrm{O}_{2}$ Thin Films by NLA at Intermediate Laser Energy Density

Autores: David Lehninger, Tianren Zhang, Peter Reinig, Justine Barbot, Mathieu Opprecht, Sébastien Kerdiles, Laurent Grenouillet, Konrad Seidel, Maximilian Lederer
Publicado en: 2025 International Conference on IC Design and Technology (ICICDT), 2025
Editor: IEEE
DOI: 10.1109/ICICDT65192.2025.11078051

DTCO of advanced FDSOI CMOS technology by process emulation

Autores: Aicha Boujnah; Olga Cueto; Marie-Anne Jaud; Sebastien Martinie; Franck Nallet; Claire Fenouillet-Beranger
Publicado en: 2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2024
Editor: IEEE
DOI: 10.1109/SISPAD62626.2024.10733323

High Performance 2.5V n&p 400°C SOI MOSFETs: a Breakthrough for versatile 3D Sequential Integration

Autores: D. Bosch, W. Vandendaele, E-A Diallo, A-S Royet, A. Albouy, M. Opprecht, F-X Darras, V. Benevent, P. Maillard, O. Adami, M. Ribotta, S. Kerdilès, R. Gassilloud, X. Garros, P. Batude
Publicado en: 2025 IEEE International Electron Devices Meeting (IEDM), 2025
Editor: IEEE
DOI: 10.1109/IEDM50572.2025.11353514

Comparative study of ALD MoS2 on high-k dielectrics for the fabrication of nanowire FETs

Autores: M. Rodriguez-Fano, J.M. Pedini, S. Cadot, H. Grampeix, T. Magis, F. Laulagnet, R. Souil, S. Barraud
Publicado en: 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024
Editor: IEEE
DOI: 10.1109/ESSERC62670.2024.10719452

Spintronic Devices for Thermodynamically Guided Analog Computing

Autores: K.-E. Harabi, K. Danouchi, L. Soumah, A. Hakam, A. Bazzi, J. Peters, H. Levices, M. A. Iftakher, N.-T. Phan, C. Bouchard, F. Disdier, E. Yildiz, R. Sousa, U. Ebels, B. Delaet, F. Badets, G. Prenat, L. Anghel, B. Viala, T. Dalgaty, D. Querlioz, I.-L. Prejbeanu, F. Andrieu, K. Garello, P. Talatchian, L. Hutin
Publicado en: 2025 Device Research Conference (DRC), 2025
Editor: IEEE
DOI: 10.1109/DRC66027.2025.11105749

First Radio-Frequency Circuits Fabricated in Top-Tier of a Full 3D Sequential Integration Process at mmW for 5G Applications

Autores: J. Lugo-Alvarez, J.B. David, A. Siligaris, V. Puyal, G. Moritz, T. Mota-Frutuoso, V. Lapras, C. Fenouillet-Beranger, L. Brunet, P. Vincent, D. Lattard, X. Garros, F. Andrieu, P. Batude
Publicado en: 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2025
Editor: IEEE
DOI: 10.1109/VLSITECHNOLOGYANDCIR46783.2024.10631483

Electronic-Grade Silicon (EG Si) Wafer Production: Review and Update of Life Cycle Inventory (LCI) Data

Autores: Enola Fidon, Suzanne Guillou, Yannick Rivoira, Laura Vauche
Publicado en: REACT 2025, 2026
Editor: MDPI
DOI: 10.3390/ENGPROC2026127016

ADVANCING MICROELECTRONICS EDUCATION: THE PEDAGOGICAL FRAMEWORK OF THE FAMES EUROPEAN FD-SOI DESIGN SCHOOL (EFDS2026)

Autores: Sana Ibrahim, Laurent Fesquet
Publicado en: EDULEARN Proceedings, EDULEARN26 Proceedings, Edición 1, 2026
Editor: IATED
DOI: 10.21125/EDULEARN.2026.0541

Impact of Cu density on via-to-via hybrid bonding: morphological and electrical characterizations

Autores: Agathe Lerat, Pablo Renaud, Christophe Dubarry, Margot Faure, Floriane Baudin, Sebastien Dominguez, Hadi Hijazi, Yorrick Exbrayat, Frank Fournel
Publicado en: 2026 IEEE 76th Electronic Components and Technology Conference (ECTC), 2026
Editor: IEEE
DOI: 10.1109/ECTC51846.2026.00345

ITO Contact Optimization for Enhancement Mode BEOL MOSFETs

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Publicado en: 2025 Device Research Conference (DRC), 2025
Editor: IEEE
DOI: 10.1109/DRC66027.2025.11105747

Silicidation of Next Generation of FD-SOI Devices: Effect of P Doping Level in epitaxial Si:P Films

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Editor: MAM2024

Robust SPICE Model for FeCap: Application to 16kbit 1T-1C FeRAM Array Simulation

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Publicado en: 2025 International Compact Modeling Conference (ICMC), 2025
Editor: IEEE
DOI: 10.1109/ICMC64879.2025.11102766

Plasma etching process tailoring for different polysilicon microstructures used in 10nm FD-SOI metal gate stacks

Autores: M. Y. Aliouat, J. Dubois, P. Pimenta-Barros, A. Sarrazin, S. Beaurepaire, O. Dubreuil, L. Couture, L. Brevard, A. Magalhaes-Lucas, T. Mota Frutuoso, M. Ribotta, C. Fenouillet-Beranger, F. Boulard
Publicado en: Advanced Etch Technology and Process Integration for Nanopatterning XV, 2026
Editor: SPIE
DOI: 10.1117/12.3090459

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Editor: IEEE
DOI: 10.1109/EUROSIME60745.2024.10491442

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Publicado en: 2026 IEEE International Reliability Physics Symposium (IRPS), 2026
Editor: IEEE
DOI: 10.1109/IRPS61424.2026.11499220

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