As a new step in SiPearl’s journey, Cronos processor targets data centre (DC) applications. During the past period, SiPearl learned about DC challenges, codes and usages. It allowed the teams to identify the key customers and suppliers.
SiPearl met potential DC customers exploring key aspects of DC operation such as workloads, AI, manageability and security. Several workshops confirmed our intuition that an ARM core-based data centre processor can make a difference for computing efficiency and power saving.
SiPearl has studied Intel and AMD processors on both capabilities and pricing, and later Amazon’s Graviton processor and Ampere computing both based on ARM processor.
SiPearl then identified key software workloads. Our approach is to run out of the box main Linux distributions to help customers. DC run a variety of software to manage the infrastructure ranking from web servers, databases, load balancers to dispatch traffic on multiple servers, virtual machines, backups. But they also run a lot of corporate appliances as ERP, dedicated software tools, private databases to multiple SaaS applications.
To lower the total cost of ownership (TCO) in DC, CPU vendors must increase the number of CPU core in a processor, meaning an increase of the silicon area in the processor. The manufacturing process limits the maximum area. When the area is too big the manufacturing defects increase the costs and lower the production output. This is where the famous Moore’s law no longer applies. The semiconductor industry responded to this by splitting big monolithic silicon dies into smaller interconnected dies, called chiplets.
The 2023 Chiplet Summit shed the light on many players in the chiplet manufacturing space. Chiplet requires special electronic design practices and new packaging manufacturing capabilities. As silicon dies can’t be soldered to printed circuit board due to the thickness (150um pitch) of the electrical connection at their surface, a substrate is needed to increase the contact size and improve the mechanical resistance. This is called a package. It transforms silicon dies into chips and allows connecting them to a PCB, and plays a critical role at the crossroad between electronics, mechanics, thermal dissipation and manufacturing. As packaging represents an important part of the total cost of Helios, choosing the right die-to-die interconnexions technology is key. SiPearl initiated discussions with its foundry (TSMC) and packaging partner but also explored many other areas:
DDR memory technology is an ever evolving technology, which directly impacts the bandwidth and computing power. Helios will implement DDR controllers IP to connect such memory sticks to it. Due to its long development cycle, SiPearl anticipates the DDR evolution to get the best technology and cost per GB for the memory plugged on our product.
PCIe is a major interface standard in computing world to interconnect processors to a device such as video cards, network interfaces cards, accelerator cards, storage controller cards, etc. SiPearl has studied and followed PCIe standard evolution both on hardware and software side and has engaged close relationship with PCIe IP vendors.
UCIe is a new kind of data interfaces dedicated to die-to-die interconnect, maintained by an industrial consortium. The first version of the standard V1.0 delivered two flavours : UCIe standard for die-to-die interconnect on substrate with a maximum tracks length of 25 mm, and UCIe advanced standard for interconnect on silicon interposer with maximum track length of 2,5 mm.
AI accelerator is also critical. AI hype pushes hyper scalers to offer to their customers dedicated servers for AI inferencing. These are build on expensive GPU accelerator. For cost optimization, an alternative is to do AI inference on CPU or on dedicated AI hardware accelerator. Helios will support both GPU and dedicated accelerator for system integration.
Through our partnership with ARM, we are assessing IP to increase the data bandwidths that a CPU core needs to meet the target computing performance. They have a major impact on Helios internal bus interconnect dimensioning, topology and die to die interfaces numbers. Our study leverages reference design, and more specifically the multi-die uses cases. It is a reliable source to confront our idea of architecture for Helios and a reference for cache coherency mechanism validation between Helios and the compute dies.
Architecture simulation also started with some performance comparison of direct architecture scheme for Helios.
