Though current day designs carry the promise of meeting the ever escalating demands of high performance/ quality requirements, they often exhibit large power consumption that limits the battery lifetime and generates excessive heat. Besides power consumption, process variations also pose major design concern with scaling of devices that may lead to erroneous computations and loss of stored data threatening the correct operation of future systems. Addressing both issues of low-power and reliable operation simultaneously is one of the most challenging design problems that semiconductor industry is facing today since they are contradictory in nature. The proposed project plans to address both issues by identifying and utilizing algorithmic level characteristics that can allow the design of systems that provide the right trade-offs between output quality, energy consumption and parametric yield under technology imperfections. The feasibility of the proposed cross-layer design methodology is demonstrated by our observation that for DSP systems, all computations are not equally important in shaping the output response. For such systems, some computations are more critical for determining the output quality, while others play a less important role. This information is exploited in this proposal to develop suitable designs for logic and memory elements of wireless systems that are the core of all today’s portable devices. Main target of the proposed project is to reduce the high cost of existing variation-aware techniques and overcome the incompatibility of most of them with DSP systems. Furthermore, in order to improve the energy efficiency of systems the proposal will take into account system level interactions trying to limit the energy wasted in various blocks that may operate unnecessarily in high power/quality modes in case of non-ideal operating conditions. The project is expected to strengthen EU research in one of the most challenging research topics.
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