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Zawartość zarchiwizowana w dniu 2024-04-15

Improvement of Yield and Performance of ICS by Design Centring

Cel

The objective of project 456 was to investigate mathematical means of shifting the parameters of a integrated circuit (IC) to a location (design centre) where they can fluctuate in a wider range without impairing the function of that circuit. This increases the fabrication yield. The same method can be used to enhance the performance of such circuits.
The objective was to investigate mathematical means of shifting the parameters of an integrated circuit (IC) to a location (design centre) where they can fluctuate in a wider range without impairing the function of that circuit. This increases the fabrication yield. The same method can be used to enhance the performance of such circuits.

An existing computer program for design centring and a program for the improvement of circuit performance were improved and adapted to the special problems occurring in the design of very large scale integration (VLSI) circuits.

The main deliverables were:
an optimisation program package, MCSPICE, based on the well know network simulator SPICE;
a user friendly interpreter and an intermediate results processor for run time control for the above program;
preprocessors and postprocessors for workstation based input and output.

The program was tested successfully on circuits with 16 parameters, but that is not thought to be the maximum limit. Example circuits and physics based models were used to test the effectiveness of the program as the basis for a real industrial design tool, with promising results.
The operating environment is as follows :
Computer aided design (CAD) and design methodologies
An existing computer program for design centring and a program for the improvement of circuit performance were improved and adapted to the special problems occurring in the design of VLSI circuits in the participating companies. The involvement of industrial firms ensured the availability of transistor models which reflect the properties of their ICfabrication lines.
The main deliverables were:
-an optimisation program package, MCSPICE, based on the well-known network simulator SPICE
-a user-friendly interpreter and an intermediate results processor for run-time control for the above program
-pre- and post-processors for workstation-based input and output.
The program was tested successfully on circuits with 16parameters, but that is not thought to be the maximum limit. Example circuits and physics-based models from the industrial partners were used to test the effectiveness of the program as the basis for a real industrial design tool, with promising results.
Although the project achieved its initial objectives, which are thought likely to be the basis of a useful industrial design facility, its continuation was not thought to belong to the precompetitive ESPRIT programme.
Exploitation
The results obtained are expected to have an impact on the industrialisation of ICs, which should be possible initially within the participating organisations.

Temat(-y)

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Zaproszenie do składania wniosków

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System finansowania

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Koordynator

Universität Stuttgart
Wkład UE
Brak danych
Adres
Pfaffenwaldring 47
70569 Stuttgart
Niemcy

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Koszt całkowity
Brak danych

Uczestnicy (3)