Periodic Reporting for period 2 - REMINDER (Revolutionary embedded memory for internet of things devices and energy reduction) Okres sprawozdawczy: 2017-07-01 do 2018-12-31 Podsumowanie kontekstu i ogólnych celów projektu To achieve the objectives of REMINDER, the project structure is founded on three mainpillars:1. Investigation (concept, design, characterization, simulation, modelling), selection andoptimization of a Floating-Body memory bit cell in terms of low power and low voltage, highreliability, robustness (variability), speed, reduced footprint and cost. Fabrication of selectedbit cells with FDSOI and III-V technologies.2. Design and fabrication in FD28 and FD14 technology nodes of a memory matrix based onthe optimized bitcells developed in the first pillar. Matrix memory subcircuits, blocks andarchitectures will be carefully analysed from the power-consumption point of view. Inaddition, variability tolerant design techniques underpinned by variability analysis andstatistical simulation technology will be considered.3. Demonstration of a system on chip (SoC) application using the developed memorysolution and benchmarking with alternative embedded memory blocks.Technical objectives• Tech 1: Investigation, selection and optimization of a memory bit cell in terms of lowpower and low voltage, high reliability, robustness (variability), speed, reducedfootprint and cost based on Floating-Body SOI concept.• Tech 2: Design and fabrication in FD28 and FD14 technology nodes of a memorymatrix based on the optimized bit-cells.• Tech 3: Demonstration of the developed memory solution and benchmarking withalternative embedded memory blocks.Scientific Objectives• Sci 1: Electrical characterization: from ultimate CMOS to Beyond Si CMOS.• Sci 2: Advanced numerical simulation: Top-down hierarchical simulation• Sci 3: Variability and reliability issues of advanced nanodevices• Sci 4: Development of ultra-low power memory solutionsStrategic Objectives• Stra 1: Reinforce the European manufacturing position by gaining leadershipthrough the demonstration of ultra-low-power IP blocks for IoT edge devices,wearables and health systems using FDSOI technologies developed bySTMicroelectronics.• Stra 2: Demonstrate the suitability of emerging III-V MOSFETs, nanowire FETs and3D circuits for ultralow-power applications, extending the FDSOI technology.• Stra 3: This project will deliver significant strategic benefit to the partners and the EUthrough the research and delivery of a new memory solution which will offercompetitive advantage to EU companies by a) improved performance, specificallylower power; b) lower cost, specifically through a simpler process and smaller area. Prace wykonane od początku projektu do końca okresu sprawozdawczego oraz najważniejsze dotychczasowe rezultaty According to the Workplan, the main objectives for the first reporting period (M1-M18) of REMINDER project were:1. Kick-off of the project.2. Selection of the memory cell among the three candidates to build an embedded memory matrix, and later, the committed demonstrator.3. Extensive electrical characterization of selected devices and calibration of TCAD tools.4. Extensive TCAD simulation of selected devices (Z2FET).5. Design and fabrication of REMINDER-dedicated devices.6. Compact modelling activities for the selected cell. 7. Starting the design of a prototype of an embedded DRAM memory matrix using Z2FET as building block.8. Simulation and characterization of 3D NWs and III-V semiconductors memory cells.9. Dissemination and Exploitation activities (publications and first industrial workshop organization).10. Continuous reporting to the EU. Innowacyjność oraz oczekiwany potencjalny wpływ (w tym dotychczasowe znaczenie społeczno-gospodarcze i szersze implikacje społeczne projektu) The semiconductor industry needs, more than ever, new memory paradigms to tackle withthe storage, processing, energy consumption and cost demands of the integrated circuitsoriented to the Internet of Things (IoT). The REMINDER project is ultimately focused todevelop an embedded Floating Body DRAM solution for IoT cut-edge devices, i.e. thepursued memory block will be optimized for ultra-low-power consumption, variabilityimmunity, and low cost, in addition to the footprint miniaturization. The pragmatic approachfor quick lab-to-market demonstration is to use the established FDSOI technology, withoutintroducing alternative materials or new steps in the fabrication process (different from theones already necessary to fabricate the rest of blocks in the system). In parallel, we will alsodefine longer-term FB-DRAM solutions using emerging technologies that are not yetestablished (III-V, NWs, and SiGe). Picture of the silicon wafer with Z2FET devices and memory matrix Schematic of a Z2FET device