An Artificial Visual Cortex for Image Processing

Informacje na temat projektu

ARTIV1

Identyfikator umowy o grant: 727283

DOI

10.3030/727283

Projekt został zamknięty

Data podpisania przez KE 27 Lutego 2017

Data rozpoczęcia 1 Kwietnia 2017

Data zakończenia 30 Września 2018

Finansowanie w ramach

• EXCELLENT SCIENCE - European Research Council (ERC)

Koszt całkowity

€ 149 937,00

Wkład UE

€ 149 937,00

Koordynowany przez

CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE CNRS
France

Periodic Reporting for period 1 - ARTIV1 (An Artificial Visual Cortex for Image Processing)

Okres sprawozdawczy: 2017-04-01 do 2018-09-30

Podsumowanie kontekstu i ogólnych celów projektu

Project overview

ARTIV1 is a project to construct and commercialise a dedicated hardware emulating the functional architecture of the visual cortex of mammals. Such hardware will have, on the one hand, a huge degree of parallelism and, on the other hand, connections among the central processing units that reflect the non-isotropic structure of the visual cortex. The hardware that we plan to build as a application-specific integrated circuit (ASIC) with an industrial partner will be a veritable artificial visual cortex. It will be fully programmable and it will be able to perform many biomimetic image processing tasks that we expect to be exceptionally performant.
We expect that ARTIV1 will come to the market accompanied by some dedicated software for image reconstruction and image recognition. However other applications will be developed in the future both by our research team and by customers, as for instance software for optical flow estimation or for sound processing (such as sound reconstruction and sound recognition).


The financial support of EU has permitted :

1) to hire an engineer for 8 months. The engineer, together with the PI, have
-) optimized the algorithm for image reconstruction that now is working on color images and has results at the state of the art in image processing;
-) started the construction of a dedicated architecture on FPGA. This is the first step to realize an ASIC with some industrial partner;
-) started to adapt the algorithm of image reconstruction to sound reconstruction in the time-frequency domain.
2) to start discussions with possible industrial partners;
3) to finance a marked analysis that clarified the possible customers and the target of possible industrial partners.