WP1: The system architecture and requirements were described thoroughly early in the project forming a solid foundation for the work carried out on passives (WP2), semiconductors (WP3), power electronics (WP4) and driver system (WP5).
The focus was split into a development track and a research track. The focus for the development track was taking the first demonstrator from lab mock-up to a full system demonstrator. It is aimed at a high technology readiness level at an attractive material cost level. The focus for the research track was to push towards a small size and lightweight LED driver. This required WP1 to cope with several different system architectures and requirements, but all based on the solid foundation designed at the beginning of the project.
WP2: A state of the art review for sputtered soft magnetic materials has identified Co Zr Ta B (CZTB) as a promising first candidate material which shows a significant improvement over the present plated material. Consequently, CZTB was the choice of material for fabricating the generation 1 magnetic devices. Laminated films of CZTB and dielectric material were fabricated and characterised in relation to their magnetic properties. The development of a patterning process for laminated CZTB stacks was completed. Generation 1 and 2 integrated magnetic devices were fabricated using CZTB as the magnetic core material.
WP3: Process selection for full integration was narrowed down to 3 options: AMS, X-FAB and ST. Discrete (e.g. naked dies) GaN FETs are identified as a potential other solution. Furthermore, integrated custom designed GaN FETs from Fraunhofer are under investigation.
A start-up circuit for the Class-E inverters from WP4 was designed, simulated, laid out and sent for production as a tape-out in the AMS 180nm, 50 V process.
WP4: The interface between the AC/DC and DC/DC was thoroughly examined early on. The tradeoffs between various nominal voltages and the allowed low frequency ripple was discussed and a high bulk voltage was used for the first demonstrator.
The D-track managed design The focus was to improve the performance, meet the full list of specs and make it mature enough for cost and lifetime evaluations.
For the R-track it was decided to shift to a low bulk voltage, as this gave a wide range of possibilities on the AC/DC and could be an opportunity to reach the objective of 90% size reduction.
WP5: A low-voltage auxiliary power supply (LVPS) and DALI interfaces was developed and tested. This was integrated with a AC/DC and DC/DC from WP4 to build a complete LED driver.
Various PWM modulation techniques were investigated. As a result of this, a solution that simultaneously fulfilled the dimming requirements and the flicker requirements according to IEEE 1789 was found.
WP5 was responsible for the evaluation of the first complete driver, the system integration for both the D- and R-track and evaluation of the complete drivers from these.
WP6: Candidate light fittings in the 18-50W range were identified and the first prototype D-track driver was demonstrated to satisfactorily drive a wide range of these fittings. The first prototype D-track driver was modified along with a surface mount LED light engine to create a daughterboard driver on board a motherboard LED light engine; the light fitting was demonstrated.
A light fitting was developed to demonstrate the advantages of the conventional LEDLUM D-track second prototype driver size and form factor. This was a linear transparent panel with side and downlighting from an aluminium spine, doubling as the driver housing and heat sink for the LEDs and the driver. The final prototype driver was demonstrated with the prototype of this fitting.
