Periodic Reporting for period 3 - 3D-MUSE (3D Multi-Process Sequential Integration for Smart Sensor Interfaces)
Okres sprawozdawczy: 2021-01-01 do 2022-09-30
The IoT is composed of connected devices that are characterized by their interaction with the environment via a plethora of sensors and actuators. The trend goes to ever more complex interactions and thus an increase in the number of different sensors integrated in the same product, which in turn requires the processing capability to handle all of those sensors.
At the same time those systems are expected to still perform on an ever lower power budget, preferably so low as to be able to operate purely on power scavenging. And of course the cost needs to be moderate too. The electronics at the heart of such a system needs to be mixed-signal electronics that interfaces to the analog sensors and actuators, but can also provide the necessary digital processing power.
3D-MUSE wants to spearhead monolithic/sequential 3D integration CMOS technology to addresses functional scaling for such mixed signal systems. In particular we shall promote the progression from what we refer to as 'systems-in-stack' to true 'systems-in-cube' that this technology shall enable. We define the former as a 3D system that is characterized by locating functional blocks within a single plain in the (typically parallel/wafer-bonding) 3D integration stack, while the latter makes use of the full emancipation of the interconnect density in the third dimension of sequential 3D integration and rather implements functional blocks in a volume comprising multiple tiers. We shall demonstrate this concept by conceiving novel architectures for micro circuits in a volume in a two tier 3D sequential integration process. In particular, we have identified mixed-signal circuits as, on one hand, a major bottleneck for functional performance scaling of sensor nodes and smart sensors in the IoT and cyberphysical systems, and on the other hand, excellent candidates for beneficial trade-offs when implemented as circuits in a volume with using two specialize tiers, one for analog device options and another for optimal digital designs. We shall refer to such a technology as 'multi-process' sequential 3D integration.
At the same time those systems are expected to still perform on an ever lower power budget, preferably so low as to be able to operate purely on power scavenging. And of course the cost needs to be moderate too. The electronics at the heart of such a system needs to be mixed-signal electronics that interfaces to the analog sensors and actuators, but can also provide the necessary digital processing power.
3D-MUSE wants to spearhead monolithic/sequential 3D integration CMOS technology to addresses functional scaling for such mixed signal systems. In particular we shall promote the progression from what we refer to as 'systems-in-stack' to true 'systems-in-cube' that this technology shall enable. We define the former as a 3D system that is characterized by locating functional blocks within a single plain in the (typically parallel/wafer-bonding) 3D integration stack, while the latter makes use of the full emancipation of the interconnect density in the third dimension of sequential 3D integration and rather implements functional blocks in a volume comprising multiple tiers. We shall demonstrate this concept by conceiving novel architectures for micro circuits in a volume in a two tier 3D sequential integration process. In particular, we have identified mixed-signal circuits as, on one hand, a major bottleneck for functional performance scaling of sensor nodes and smart sensors in the IoT and cyberphysical systems, and on the other hand, excellent candidates for beneficial trade-offs when implemented as circuits in a volume with using two specialize tiers, one for analog device options and another for optimal digital designs. We shall refer to such a technology as 'multi-process' sequential 3D integration.
The first 18 months period has been dedicated to 3D sequential technology development as well as the corresponding design tools, has culminated in a 3D sequential integration (3DSI) tape-out. The second period has been dedicated to development of the 3DSI processes and to completing the processing the bottom tier, as well as to extending the architectures developed for the tape-out in simulation. In the final period the 3DSI processing has passed all critical development steps (up to depositing metal 5) and started with the remaining standard metal layer deposition steps (up to metal 7 complete, of a total of 10 metal layers). Some basic electrical testing on the wafer after metal 6 deposition show functional transistors and 3D-connections. Full characterization has not been completed at this point though! Furthermore, a number of publications explore the 3DSI circuit architectures in simulation using the 3D-MUSE PDKs, show casing the potential of this technology.
New features have been added to sequential 3D CMOS integration technology, in particular 1) a shallow trench polysilicon insolation layer between the bottom tier and the top tier to enable free placement of sensitive analog circuits on top of digital circuits without having to worry about coupling noise, and 2) A high voltage FET device option for the top tier suitable for analog applications. Also, the 3D sequential technology demands circuit design software tools that are somewhat different from traditional 2D tools and two 'process development kits' (PDK) have been implemented for that purpose. These tools have been used to design a few circuit modules for the 3D-MUSE production run that started to scratch the surface of the benefits that can be reaped from the very dense 3D interconnect this technology offers. Ever more advanced circuits and system concepts have subsequently been explored in simulation during the second and third project period. The process development steps are now complete and basic device functionality affirmed, with some standard processing remaining. The partners await the finished dies in Spring/Sunmer 2023 and will dedicate their own resources to full characterization and testing. The project investigates in particular mixed-signal integrated circuits, i.e. systems and circuits suited for IoT devices that interface with the real world through various sensors. Simulation based scientific publications explore the potential of the technology.
New features have been added to sequential 3D CMOS integration technology, in particular 1) a shallow trench polysilicon insolation layer between the bottom tier and the top tier to enable free placement of sensitive analog circuits on top of digital circuits without having to worry about coupling noise, and 2) A high voltage FET device option for the top tier suitable for analog applications. Also, the 3D sequential technology demands circuit design software tools that are somewhat different from traditional 2D tools and two 'process development kits' (PDK) have been implemented for that purpose. These tools have been used to design a few circuit modules for the 3D-MUSE production run that started to scratch the surface of the benefits that can be reaped from the very dense 3D interconnect this technology offers. Ever more advanced circuits and system concepts have subsequently been explored in simulation during the second and third project period. The process development steps are now complete and basic device functionality affirmed, with some standard processing remaining. The partners await the finished dies in Spring/Sunmer 2023 and will dedicate their own resources to full characterization and testing. The project investigates in particular mixed-signal integrated circuits, i.e. systems and circuits suited for IoT devices that interface with the real world through various sensors. Simulation based scientific publications explore the potential of the technology.
Classical 3D integration technology has already conquered the market for various consumer applications, foremost for image sensors where the Sony Exmor sensor family uses parallel 3D integration already to great advantage. Sequential/monolithic 3D integration is positioned to take that development to the next level by increasing the 3D connection density by about one order of magnitude and thus enabling circuit design concepts that truly exploit a 3D volume rather than stacking multiple 2D functional circuit blocks. During the past 57 month 3D-MUSE has been starting to design such 'Systems-in-Cube' for various sensor node and IoT applications vying to grant European industry a head start in this fast-moving market, and steady progress is being made for a demonstrator of the technology in real silicon. In late 2022, both Sony and STM have published monolithic/sequential 3D integration demonstrators for CMOS image sensors in particular, so this seems to be the markert segment to first embrace the concept.