Rezultaty
Report on proof of concept realization.
ST 28nm bottom tier processing finishedDelivery of the bottom strata composed of FDSOI technology MOSFET and 4 metal line levels
2nd 18 month period report
Final ReportFinal report to the comission
Test and test report from TDC in 3D SinCIDEAS will work on testing the TDC circuit with respect to the target specifications They will design a circuit board to test the circuits
Specification for the analog MOSFETSpecification for visible image sensor (supply voltage, noise, hot carrier injection, reliability specifications) Cost evaluation of the low cost version of FDSOI dedicated for the analog layer and comparison with the standard BULK technology
Low-temperature high-voltage analog MOSFET characterizationDeep analysis of low temperature analog MOSFET, conclusions on the process performance adequation with ST specifications
Periodic Project report 11st 18 month period report
Test report physical implementation SinC modulesThe SinCSSI modules that havbe been physically produced by ST and LETI shall be tested and characterized and their performance compared to StoA
A project web-page will be established and a system will be worked out to allow partners to edit and contribute to the cite. The structure will be finished by m6 but the content will be edited throughout the project live time.
The purpose of the data management plan (DMP) is to define the main elements of the data management policy that will be used by the 3D-MUSE consortium partners with regard to all the datasets that will be generated within the project. As part of the dissemination and exploitation activities, the 3D-MUSE DMP will be drafted and updated during the execution of the project, i.e., it is not a fixed document, but evolves during the lifespan of the project. Updates will be reported with the periodic project reports. In accordance with the H2020 guideline, the 3D-MUSE DMP outlines how research data will be handled during project execution, and after its completion, i.e., post-project, essentially along the lines of exploitation and commercialisation.
Publikacje
Autorzy:
T. A. Karatsori, C. Cavalcante, J. Lacord, P. Batude, C. Theodorou, G. Ghibaudo
Opublikowane w:
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2019, Strona(/y) 1-2, ISBN 978-1-7281-3523-6
Wydawca:
IEEE
DOI:
10.1109/s3s46989.2019.9320739
Autorzy:
C. Cavalcante, X. Garros, P. Batude, A. Tataridou, J. Lacord, M. Casse, C. Theodorou, T. Karatsori, R. Gassilloud, C. Fenouillet-Beranger, L. Brunet, O. Rozeau, N. Rambal, F. Gaillard, F. Ponthenier, F. Allain, G. Romano, G. Ghibaudo, J-P. Colinge, M. Vinet, F. Andrieu
Opublikowane w:
2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2020, Strona(/y) 155-156, ISBN 978-1-7281-4232-6
Wydawca:
IEEE
DOI:
10.1109/vlsi-tsa48913.2020.9203691
Autorzy:
C. Cavalcante, C. Fenouillet-Beranger, P. Batude, X. Garros, X. Federspiel, J. Lacord, S. Kerdiles, A. S. Royet, P. Acosta-Alba, O. Rozeau, V. Barral, F. Arnaud, N. Planes, P. O. Sassoulas, E. Ghegin, R. Beneyton, M. Gregoire, O. Weber, C. Guerin, L. Arnaud, S. Moreau, R. Kies, G. Romano, N. Rambal, A. Magalhaes, G. Ghibaudo, J. P. Colinge, M. Vinet, F. Andrieu
Opublikowane w:
2020 IEEE Symposium on VLSI Technology, 2020, Strona(/y) 1-2, ISBN 978-1-7281-6460-1
Wydawca:
IEEE
DOI:
10.1109/vlsitechnology18217.2020.9265075
Autorzy:
O. Billoint, K. Azizi-Mourier, G. Cibrario, D. Lattard, M. Mouhdach, S. Thuries, P. Vivet
Opublikowane w:
2019 International 3D Systems Integration Conference (3DIC), 2019, Strona(/y) 1-5, ISBN 978-1-7281-4870-0
Wydawca:
IEEE
DOI:
10.1109/3dic48104.2019.9058793
Autorzy:
C. Fenouillet-Beranger, L. Brunet, P. Batude, L. Brevard, X. Garros, T. Mota Frutuoso, M. Casse, J. Lugo, J. Lacord, D. Bosch, N. Bernard, A. Magalhaes-Lucas, M. Ribotta, B. Sklenard, F. Milesi, R. Kies, G. Romano, P. Acosta-Alba, S. Kerdiles, A. Tavernier, C. Vizioz, P. Besson, R. Gassilloud, J. Kanyandekwe, D. Cooper, V. Lapras, W. H. Kim, Y. Sasaki, S. Oh, P. Kang, S. W. Lee, H. Na, J. Arcamone
Opublikowane w:
2020 IEEE Symposium on VLSI Technology, 2020, Strona(/y) 1-2, ISBN 978-1-7281-6460-1
Wydawca:
IEEE
DOI:
10.1109/vlsitechnology18217.2020.9265092
Autorzy:
F. Andrieu, P. Batude, L. Brunet, C. Fenouillet-Beranger, D. Lattard, S. Thuries, O. Billoint, R. Fournel, M. Vinet
Opublikowane w:
2018 International Conference on IC Design & Technology (ICICDT), 2018, Strona(/y) 141-144, ISBN 978-1-5386-2550-7
Wydawca:
IEEE
DOI:
10.1109/icicdt.2018.8399776
Autorzy:
L. Brunet, C. Fenouillet-Beranger, P. Batude, S. Beaurepaire, F. Ponthenier, N. Rambal, V. Mazzocchi, J-B. Pin, P. Acosta-Alba, S. Kerdiles, P. Besson, H. Fontaine, T. Lardin, F. Fournel, V. Larrey, F. Mazen, V. Balan, C. Morales, C. Guerin, V. Jousseaume, X. Federspiel, D. Ney, X. Garros, A. Roman, D. Scevola, P. Perreau, F. Kouemeni-Tchouake, L. Arnaud, C. Scibetta, S. Chevalliez, F. Aussenac, J
Opublikowane w:
2018 IEEE International Electron Devices Meeting (IEDM), 2018, Strona(/y) 7.2.1-7.2.4, ISBN 978-1-7281-1987-8
Wydawca:
IEEE
DOI:
10.1109/iedm.2018.8614653
Autorzy:
P. Batude, L. Brunet, C. Fenouillet-Beranger, F. Andrieu, J.-P. Colinge, D. Lattard, E. Vianello, S. Thuries, O. Billoint, P. Vivet, C. Santos, B. Mathieu, B. Sklenard, C.-M. V. Lu, J. Micout, F. Deprat, E. Avelar Mercado, F. Ponthenier, N. Rambal, M.-P. Samson, M. Casse, S. Hentz, J. Arcamone, G. Sicard, L. Hutin, L. Pasini, A. Ayres, O. Rozeau, R. Berthelon, F. Nemouchi, P. Rodriguez, J.-B. Pin,
Opublikowane w:
2017 IEEE International Electron Devices Meeting (IEDM), 2017, Strona(/y) 3.1.1-3.1.4, ISBN 978-1-5386-3559-9
Wydawca:
IEEE
DOI:
10.1109/iedm.2017.8268316
Autorzy:
Pascal Vivet, Sebastien Thuries, Olivier Billoint, Sylvain Choisnet, Didier Lattard, Edith Beigne, Perrine Batude
Opublikowane w:
2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018, Strona(/y) 157-160, ISBN 978-1-5386-9562-3
Wydawca:
IEEE
DOI:
10.1109/icecs.2018.8617955
Autorzy:
Pascal Vivet, Gilles Sicard, Laurent Millet, Stephane Chevobbe, Karim Ben Chehida, Luis Angel Cubero, Monte Alegre, Maxence Bouvier, Alexandre Valentian, Maria Lepecq, Thomas Dombek, Olivier Bichler, Sebastien Thuries, Didier Lattard, Cheramy Severine, Perrine Batude, Fabien Clermidy
Opublikowane w:
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, Strona(/y) 674-679, ISBN 978-3-9819263-2-3
Wydawca:
IEEE
DOI:
10.23919/date.2019.8714886
Autorzy:
S. Cheramy, A. Jouve, C. Fenouillet-Beranger, P. Batude, M. Vinet
Opublikowane w:
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018, Strona(/y) 1-5, ISBN 978-1-5386-7627-1
Wydawca:
IEEE
DOI:
10.1109/s3s.2018.8640158
Autorzy:
T.A. Karatsori, K. Bennamane, G. Ghibaudo
Opublikowane w:
Solid-State Electronics, Numer 168, 2020, Strona(/y) 107722, ISSN 0038-1101
Wydawca:
Pergamon Press Ltd.
DOI:
10.1016/j.sse.2019.107722
Autorzy:
Laurent Brunet, Perrine Batude, Claire Fenouillet-Beranger, Maud Vinet
Opublikowane w:
ECS Transactions, Numer 85/8, 2018, Strona(/y) 125-130, ISSN 1938-5862
Wydawca:
Electrochemical Society, Inc.
DOI:
10.1149/08508.0125ecst
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