Descrizione del progetto
L’incollaggio di materiali avanzati rivoluzionerà l’integrazione fotonica
La tecnologia di integrazione fotonica combina vari componenti come laser, modulatori e rivelatori su un unico chip. Il progetto PICTURE, finanziato dall’UE, intende sviluppare una tecnologia di integrazione fotonica avanzata mediante l’incollaggio di più piastrine di materiale semiconduttore realizzate con materiali compositi III-V sopra wafer di silicio su isolante. Questa piattaforma di integrazione eterogenea consentirà di realizzare laser, fotorivelatori, modulatori MOSCAP III-V/Si e laser a retroazione distribuita con lunghezza d’onda sintonizzabile. L’intero processo sarà eseguito su una linea CMOS R&S da 200 mm, con conseguente aumento della resa, riduzione dell’impronta e taglio dei costi dei circuiti integrati fotonici (PIC). PICTURE svilupperà inoltre laser a punti quantici facendoli crescere direttamente su template incollati, con l’obiettivo di migliorare le prestazioni dei futuri PIC ad alta densità.
Obiettivo
The objective of PICTURE project is to develop a photonic integration technology by bonding multi-III-V-dies of different epitaxial stacks to SOI wafers with a thinner and uniform dielectric bonding layer. This heterogeneous integration platform will enable higher performance lasers and photo-detectors using the optimized III-V dies. In addition, the thinner bonding layer will lead to record performance MOSCAP III-V/Si modulators, and to a new generation of wavelength tunable distributed feedback lasers. Moreover the full process including SOI process, bonding, III-V and back-end process will be made on a 200mm R&D CMOS line, leading to higher yield, smaller footprint and lower cost PICs. Two types of PICs with a total capacity of 400Gb/s will be developed, packaged and validated in system configuration.
In parallel, PICTURE project will develop direct growth of high performance quantum-dot lasers and selective area growth on bonded templates for high density future generation of PICs.
The project is coordinated by III-V Lab, and includes University of Southampton, CEA, University College London, Imec, Tyndall, Argotech and Nokia Bell Labs. The consortium is highly complementary, covering all skills required to achieve the project objectives: growth of semiconductor materials, silicon process and III-V process, design and characterization of PICs, prototyping and assessment of PICs in high bit rate digital communication systems:
Apart from the adequacy of the consortium to achieve collectively the project objectives, the consortium partners have the potential to set up a comprehensive supply chain for the future exploitation of the project results, either by exploiting the results “in house” or by setting up suitable partnerships.
Campo scientifico
- engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringsensorsoptical sensors
- engineering and technologynanotechnologynano-materialstwo-dimensional nanostructures
- natural sciencesphysical scienceselectromagnetism and electronicssemiconductivity
- natural scienceschemical sciencesinorganic chemistrymetalloids
- natural sciencesphysical sciencesopticslaser physics
Parole chiave
Programma(i)
Argomento(i)
Meccanismo di finanziamento
RIA - Research and Innovation actionCoordinatore
91767 Palaiseau Cedex
Francia