ECHO-core.
In the front-end of the core, we developed the Entagling instruction prefetcher, a novel prefetching technique that won the 1st Instruction Prefetching Championship, 2020 [IEEE CAL'20]. Prefetching is another example of changing the future of events in a computer. We showed that, with a very low cost, Entangling brings 10% speedup on a large set of applications [ISCA'21].
In the back-end, we developed a selective and aggressive prefetcher that virtually removes store-buffer related stalls (95.0%) [Store Prefetch Bursts, MICRO'20]. We also proposed a speculative solution to enable store-to-load forwarding transparent to the programmer [Store atomicity, MICRO'20]. This solution is a first step towards an efficient implementation of Sequential Consistency. As a continuation, and in synergy with ECHO-htrg, we enabled inter-thread store to load forwarding [ITSLF, MICRO'21] allowing fast data communication between threads resulting in 12% speedup for communication-intensive applications. ITSLF was awarded an Honorable Mention at Micro TopPicks 2022 (i.e. among the 24 more relevant computer architecture papers in 2021). We removed the fences surrounding atomic operations [Free Atomics, ISCA'22, best paper sesion] resulting in 25% performance improvement when running 32 threads. Our prefetcher, BLUE, won the 1st ML-Based Data Prefetching Competition, and a follow up data prefetcher [Berti, MICRO'22] improved performance by 3.5% over the state-of-the-art.
ECHO-sync.
While analyzing programs critical sections, we found out room for improvements in the applications by using modern programming constructs. We proposed Splash-4 [ISPASS'21, IISWC'22], that reduce the execution time by 48% compared to their previous version, Splash-3. Then, targeting medium-size critical sections, we proposed MAD atomics [MICRO'21] which achieve non-speculative, non-deadlocking and concurrent execution of critical sections, thus improving performance by 2.7 times for a set of applications and concurrent data structures over an Intel RTM-like design. In parallel and in synergy with ECHO-core, we proposed delaying stores at the store buffer in hardware transactional memory [DeTraS, IEEE TPDS'22], which brings speedups of 25% for the STAMP benchmarks.
ECHO-comp.
We proposed Regional Out of Order Writes [ROOW, PACT'20], which shows that the store buffer limitations can also be addressed with a compiler that delimits safe regions of code in which stores can be reordered without breaking consistency. We also developed a compiler approach to non-speculative execution that removes important security vulnerabilities, and show that we can reduce the performance gap to an unsafe baseline by 53% (on average). Recently, we have reduced conflict misses in hardware transaction memory using a prefetching mechanism directed by the compiler [SUPE'22]. In synergy with ECHO-core, we proposed a fusion mechanism for non-contiguous instructions [MICRO'22], able to improve performance over state of the art fusion by 7%.
ECHO-htrg.
Our efficient coherence-based strict persistency work [TSOPER, HPCA'21] leverages the cache coherence protocol to provides ordering of writes in persistent memory without needing the programmer or compiler to be concerned about false sharing, data-race-free semantics, etc. We also explored efficient SIMD instructions with compiler support [TPDS'22] by compacting and restoring data used by vector operations offering speedup of 29% for a a set of applications with predicated execution.
