The project is organized around three generations (Gen) of devices, following the standard workload of semiconductor device development. During the first two year, the goal was threefold:
• Fully design, manufacture and characterize the first Gen of devices, focusing on individual building blocks (BBs): single wavelength lasers (starting TRL3), modulators (TRL1), semiconductor optical amplifiers (SOA, TRL2) and passive waveguides (TRL2).
• Elaborate consortium-wise a main and a back-up fabrication routes for the source and receiver PICs, by bringing together constraints from the design, front-end and back-end fabrication.
• Setup the infrastructure for efficient collaborative work.
An important analysis of Long Wave Infrared window for FSO communications, and subsequent specifications for cFLOW output devices was produced during the first year. Turbulence mitigation and coherent communication make LWIR potentially very competitive with 1.55µm links, but a quantum leap on technology is necessary: cFLOW rationale and objectives are confirmed with a renewed ambition.
During the first year, the main output was MS1. It consists in a DFB-QCLs working at 300 K and in continuous wave with >50 mW output power. Due to fabrication problems, this MS has been postponed to T0+15, iI was provided by partner MIRS to the full consortium (CNRS, KTH) for setting up their characterization benches and preliminary tests.
All other individual BBs were extensively designed, with promising performances for lowest TRL ones (modulator and SOAs). However, a major epitaxy problem appeared at the consortium level: the main Molecular Beam Epitaxy (MBE) reactor at III-V Lab broke down and the backup reactor at TUW couldn’t exploit pre-grown samples from III-V Lab. Results was a year without any dedicated sample. For these reasons, we asked for an amendment to extend by nine months the duration of the project cFLOW from 42 months to 51 months. Three months are due to COVID19 crisis and six months are due to a double breakdown of the project main and back-up epitaxy reactors.
The main achievement in the second year is the growth of fourteen structures and a total of 37 wafers. It is large enough for most of processing activities in cFLOW in 2021. The only structure that we didn’t have time to grow was strain compensated layers for high speed QCL (task 3.2). Another challenge is to re-grow a 3-6 μm thick InGaAs/InP structure that would be a world-first demonstration. Preliminary tests on MOVPE started in Feb 2020 but were interrupted due to COVID 19 and were postponed since.
The second objective (PIC architecture elaboration) has been pushed ahead of schedule while fabrication was on hold: this side of MS2 has been reached in a satisfactory manner, through intense discussion between partners to share their interfaces and constraints. The processing are going on at MRS, TUW and III-V Lab clean rooms for SOA, QCDs, modulators and QCLDs. The components are expected mid-2021 with results on time for the next growth campaign dedicated to Gen 2 devices.
Next generation of devices depend on several technical choices that we still have to make and validate. It concerns:
- Modulator design;
- Opportunities to regrow butt-join un-doped InGaAs / InP to limit losses in dielectric waveguides;
- MBE growth and strain compensated structures for rapid QCL
At last, the consortium as successfully set-up all infrastructure for efficient work and collaboration:
• 4 PhD were recruited to work on the project (3 on own partners funds, on top of the EC grant).
• Basic communication tools are setup (website, social networks… ) and will be ramped-up when the project starts delivering consistent results.
• Efficient information exchange in between partners has been allowed by a common server.
• The consortium agreement has been signed.
