Periodic Reporting for period 2 - AMPERE (A Model-driven development framework for highly Parallel and EneRgy-Efficient computation supporting multi-criteria optimisation)
Okres sprawozdawczy: 2021-07-01 do 2023-06-30
Cyber-Physical Systems (CPS) demand high levels of performance, operating within small power envelopes (with operational temperature constraints in many cases), while satisfying the non-functional requirements imposed by the application domain such as real-time response, resiliency, safety and security. These performance requirements can be obtained from the computational power provided by energy-efficient and highly parallel heterogeneous processor architectures including many-cores and DSP fabrics, GPUs and FPGA-based accelerator devices.
AMPERE addresses the software productivity gap existing between the complexity of the software systems required to efficiently exploit the performance capabilities of these advanced processor architectures, and the low software development productivity when addressing these type of architectures (see Figure below). This gap is further exhacerbated by the difficulty of fulfilling the non-functional requirements imposed by the cyber-physical system in the presence of parallel execution.
The AMPERE project has addressed this gap by developing an innovative software architecture that helps unleash the efficient use of parallel and heterogeneous processor architectures for automotive and railway systems, by bridging the gap between the model driven engineering techniques currently used to develop CPS and theparallel programming models used to exploit parallel architectures in the High-Performance Computing (HPC) domain.
The AMPERE software architecture implements the complete value chain for the development, deployment and efficient execution of cyber-physical systems, while guaranteing the non-functional requirements imposed by the system, by providing solutions for system integrators and end-users who need to incorporate energy-efficiency and parallel computing into their CPS. The following objectives have been achieved:
i Facilitate the design, development and maintenance of CPS implemented with modeldriven engineering targeting parallel and heterogeneous architectures.
ii Develop a set of synthesis methods for deriving efficient parallel source codes from the model driven engineering description of the system, while performing a multi-criteria optimization model transformation.
iii Develop run-time techniques for monitoring the fulfillment of functional and non-functional constraints while optimising the parallel computation.
iv Integrate the AMPERE software ecosystem within the development environments of the AMPERE parterns BOSCH and GTSI and use it to develop, deploy and efficiently execute automotive and railway applications on two parallel and heterogeneous platforms, the NVIDIA Jetson AGX Xavier and the Xilinx Zynq Ultrascale+ ZCU102.
v. Analyse the suitability of the AMPERE technology on the requirements imposed by industrial standards, and implement extensions on the model driven engineering currently HPC parallel programming models considered in the project.
AMPERE addresses the software productivity gap existing between the complexity of the software systems required to efficiently exploit the performance capabilities of these advanced processor architectures, and the low software development productivity when addressing these type of architectures (see Figure below). This gap is further exhacerbated by the difficulty of fulfilling the non-functional requirements imposed by the cyber-physical system in the presence of parallel execution.
The AMPERE project has addressed this gap by developing an innovative software architecture that helps unleash the efficient use of parallel and heterogeneous processor architectures for automotive and railway systems, by bridging the gap between the model driven engineering techniques currently used to develop CPS and theparallel programming models used to exploit parallel architectures in the High-Performance Computing (HPC) domain.
The AMPERE software architecture implements the complete value chain for the development, deployment and efficient execution of cyber-physical systems, while guaranteing the non-functional requirements imposed by the system, by providing solutions for system integrators and end-users who need to incorporate energy-efficiency and parallel computing into their CPS. The following objectives have been achieved:
i Facilitate the design, development and maintenance of CPS implemented with modeldriven engineering targeting parallel and heterogeneous architectures.
ii Develop a set of synthesis methods for deriving efficient parallel source codes from the model driven engineering description of the system, while performing a multi-criteria optimization model transformation.
iii Develop run-time techniques for monitoring the fulfillment of functional and non-functional constraints while optimising the parallel computation.
iv Integrate the AMPERE software ecosystem within the development environments of the AMPERE parterns BOSCH and GTSI and use it to develop, deploy and efficiently execute automotive and railway applications on two parallel and heterogeneous platforms, the NVIDIA Jetson AGX Xavier and the Xilinx Zynq Ultrascale+ ZCU102.
v. Analyse the suitability of the AMPERE technology on the requirements imposed by industrial standards, and implement extensions on the model driven engineering currently HPC parallel programming models considered in the project.
AMPERE has developed an innovative software architecture including the following components (see the diagram of the architecture below):
• Two Domain Specific Modeling Languages (DSML), i.e. Capella and Amalthea, that facilitate the description of the functional and non-functional behaviour of the system, independently of the underlying platform. The DSMLs have been extended with new features to better describe its parallel nature and its non-functional requirements.
• A set of code synthesis mechanisms integrated in the APP4MC framework capable of automatically transforming the DSML describing a wide variety of system configurations to parallel source code supporting:
o the OpenMP parallel programming model and dynamic partial reconfiguration of FPGA bitstreams through FRED,
o the ROS and MicroROS frameworks to communicate between hypervisor partitions.
• An extended OpenMP programming language to support very fine-grain parallelism and redundant execution through task-level replication to enhance system resiliency, by efficiently taking benefit of the parallel capabilities the underlying platform.
• A set of compiler analysis tools, implemented on top of the LLVM compilation framework capable of extracting the parallel structure of the system described with the DSML in the form of a Task Dependency Graph (TDG), which enables the optimization of several OpenMP run-time overheads and enables checking data-races in the parallel code.
• A run-time environment that constantly monitors time and energy, and adapts the execution to better fulfil the non-functional requirements and a hypervisor and a set of operating system festures that provide safety and security mechanisms, while supporting the OpenMP parallel execution model.
• A multi-criteria analysis tool-chain that optimises the timing and energy behaviour of the OpenMP program transformed from the DSML description and characterized in the TDG for interfacing the different analysis tools .
The AMPERE software architecture has been used to develop, deploy and execute two use-cases from the automotive and railway domains:
• The AMPERE partner BOSCH harnesses AMPERE technology to explore parallelization methods that leverage the better performance unlocked by heterogenous Systems-On-Chip with hardware accelerators. This has been demonstrated for a Predictive rCuise-Control application that paves the way for energy-efficient driving by configuring the drying strategy based on data analytics and Al.
• Ground Transportation Italia's Obstacle Detection and Avoidance System uses complex sensors, tracking algorithms and machine learning processes to reduce accidents and to improve passenger safety. This system demonstrates and evaluates the performance capabilities and fulfilment of non-functional requirements of AMPERE technology.
• Two Domain Specific Modeling Languages (DSML), i.e. Capella and Amalthea, that facilitate the description of the functional and non-functional behaviour of the system, independently of the underlying platform. The DSMLs have been extended with new features to better describe its parallel nature and its non-functional requirements.
• A set of code synthesis mechanisms integrated in the APP4MC framework capable of automatically transforming the DSML describing a wide variety of system configurations to parallel source code supporting:
o the OpenMP parallel programming model and dynamic partial reconfiguration of FPGA bitstreams through FRED,
o the ROS and MicroROS frameworks to communicate between hypervisor partitions.
• An extended OpenMP programming language to support very fine-grain parallelism and redundant execution through task-level replication to enhance system resiliency, by efficiently taking benefit of the parallel capabilities the underlying platform.
• A set of compiler analysis tools, implemented on top of the LLVM compilation framework capable of extracting the parallel structure of the system described with the DSML in the form of a Task Dependency Graph (TDG), which enables the optimization of several OpenMP run-time overheads and enables checking data-races in the parallel code.
• A run-time environment that constantly monitors time and energy, and adapts the execution to better fulfil the non-functional requirements and a hypervisor and a set of operating system festures that provide safety and security mechanisms, while supporting the OpenMP parallel execution model.
• A multi-criteria analysis tool-chain that optimises the timing and energy behaviour of the OpenMP program transformed from the DSML description and characterized in the TDG for interfacing the different analysis tools .
The AMPERE software architecture has been used to develop, deploy and execute two use-cases from the automotive and railway domains:
• The AMPERE partner BOSCH harnesses AMPERE technology to explore parallelization methods that leverage the better performance unlocked by heterogenous Systems-On-Chip with hardware accelerators. This has been demonstrated for a Predictive rCuise-Control application that paves the way for energy-efficient driving by configuring the drying strategy based on data analytics and Al.
• Ground Transportation Italia's Obstacle Detection and Avoidance System uses complex sensors, tracking algorithms and machine learning processes to reduce accidents and to improve passenger safety. This system demonstrates and evaluates the performance capabilities and fulfilment of non-functional requirements of AMPERE technology.
The AMPERE software architecture has achieved the following main results:
• Reduction of 30% on the software development costs, while providing the required performance and energy budget imposed by system, providing the following software architectures features:
o it hides the complexity of the technology and optimizations,
o it avoids the complex, error-prone, and time-consuming task of parallel and heterogeneous programming,
o it avoids estimating the impact of time and energy in presence of parallel execution,
o it does not require mastering on the parallel and heterogeneous technologies.
• The required performance for use-cases has been provided, with up to 3x of performance speed-up for certain use-case components, and a system utilization of 100% when redundant execution is activated, guaranteeing the fulfilment of the non-functional requirements.
• Extensions to AMALTHEA and CAPELLA has been provided to better capture the parallel and non-functional requirements of the system, including dedicated directives to instruct the synthesis tool to exploit parallelism, specializations to support multiple implementations of system functionalities and safety related information using (A)SIL terminology to support replication.
• New extensions to the OpenMP parallel programming framework targeting cyber-physical systems under revision by the OpenMP Language Committee.
• Reduction of 30% on the software development costs, while providing the required performance and energy budget imposed by system, providing the following software architectures features:
o it hides the complexity of the technology and optimizations,
o it avoids the complex, error-prone, and time-consuming task of parallel and heterogeneous programming,
o it avoids estimating the impact of time and energy in presence of parallel execution,
o it does not require mastering on the parallel and heterogeneous technologies.
• The required performance for use-cases has been provided, with up to 3x of performance speed-up for certain use-case components, and a system utilization of 100% when redundant execution is activated, guaranteeing the fulfilment of the non-functional requirements.
• Extensions to AMALTHEA and CAPELLA has been provided to better capture the parallel and non-functional requirements of the system, including dedicated directives to instruct the synthesis tool to exploit parallelism, specializations to support multiple implementations of system functionalities and safety related information using (A)SIL terminology to support replication.
• New extensions to the OpenMP parallel programming framework targeting cyber-physical systems under revision by the OpenMP Language Committee.