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Zawartość zarchiwizowana w dniu 2024-06-18

SYNthesis using Advanced Process Technology Integrated in regular Cells, IPs, architectures, and design platforms

Opis projektu


Design of semiconductor components and electronic based miniaturised systems
Synaptic project targets the optimisation of manufacturability and the reduction of systematic variations in nanometer technologies

Synaptic project targets the optimisation of manufacturability and the reduction of systematic variations in nanometer technologies through exploitation of regularity at the architectural, structural, and geometrical levels. The project proposes the creation of a methodology and associated suite of design tools which extract regularity at the architectural and structural level and automate the creation of regular compound cells which implement the functionality of the extracted templates.

The cell creation will employ Restricted Design Rules (RDR’s) and other regularity techniques at the geometrical level to maximise manufacturability and reduce systematic variations. Since the majority of designs in the nanometer regime employ some form of embedded SRAM, the project will include a study of the effects of RDR’s on SRAM in terms of performance and manufacturability and the subsequent definition of a set of RDR’s, which allow manufacturability optimisation for logic functions while remaining compatible with SRAM design rules.

To this end, the project has assembled a consortium of leading academic, research and industrial experts with world class experience in regularity approaches at the various levels. The Synaptic consortium is composed of eight leading institutions, including four European technology companies, a European world-leading research institute in the field of nanoeletronics, and three academic institutions, two from Europe and one from Brazil. In order to ensure the successful commercialisation and deployment of the resulting tool suite the consortium includes a European EDA vendor with significant expertise in the field of design optimisation through automated cell creation. This project will enable European industry to play a leading role in the definition of next-generation design methodologies.

This proposal addresses Objective ICT-2009.3.2: "Design of Semiconductor Components and Electronic Based Miniaturized Systems" by development of "methods and tools to cope with the design challenges in the next generations of technologies" and focuses on the objective "design for manufacturability taking into account increased variability of new processes". The project described in this proposal targets the optimization of manufacturability and the reduction of systematic variations in nanometer technologies through exploitation of regularity at the architectural, structural, and geometrical levels. We propose the creation of a methodology and associated suite of design tools which extract regularity at the architectural and structural level and automate the creation of regular compound cells which implement the functionality of the extracted templates. The cell creation will employ Restricted Design Rules (RDR's) and other regularity techniques at the geometrical level to maximize manufacturability and reduce systematic variations. Since the majority of designs in the nanometer regime employ some form of SRAM the project will include a study of the effects of RDR's on SRAM in terms of performance and manufacturability and the subsequent definition of a set of RDR's which allow manufacturability optimization for logic functions while remaining compatible with SRAM technologies. To this end we have assembled a consortium of European academic, research and industrial experts with world class experience in regularity approaches at the various levels. In order to ensure the successful commercialization and deployment of the resulting tool suite the consortium includes a European EDA vendor with significant expertise in the field of design optimization through automated cell creation. This project will enable European industry to play a leading role in the definition of next generation design methodologies and challenge the US domination in the area of design automation.

Zaproszenie do składania wniosków

FP7-ICT-2009-4
Zobacz inne projekty w ramach tego zaproszenia

Koordynator

STMICROELECTRONICS SRL
Wkład UE
€ 773 295,00
Adres
VIA C.OLIVETTI 2
20864 Agrate Brianza
Włochy

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Region
Nord-Ovest Lombardia Monza e della Brianza
Rodzaj działalności
Private for-profit entities (excluding Higher or Secondary Education Establishments)
Kontakt administracyjny
MARIA GRAZIA PODESTA' (Dr.)
Linki
Koszt całkowity
Brak danych

Uczestnicy (7)