WP1: The main effort has been devoted to SiC plasma etching for obtaining long and with vertical sidewalls NWs. A thorough bibliography study and plasma etching experiments under different process conditions has been performed. The experimental study was mainly dedicated to investigate various mask materials and to the effect of substrate RF power. The results of this study will be included in two chapters of a SiC-technology related book.
A major conclusion of this effort was that the lift-off process results in inclined mask sidewalls and edge mask erosion results in the pyramidal shape. In order to obtain vertical metal mask sidewalls, a nanoimprint lithography (NIL) process has been adopted as solution. A special process has been applied to narrow the diameter of the resulting SiC NWs after the plasma etching. The process resulted in 100nm diameter NWs.
WP2: Ohmic contacts: the effect of annealing in various environments (vacuum 10-5 Torr, vacuum 10-2 with small Ar forming gas flow through needle valve, atmospheric pressure in Ar forming gas ambient) was found not so important as the annealing temperature and duration.
Separation of vertical SiC NWs from their substrate: The process is necessary for fabricating horizontal back-gated NWFETs from vertical top-down (plasma etching) formed long SiC NWs. The optimized cut has been performed by loading the nanopillars in an IPA bath in downright position and by performing a sonication process.
NW diameter narrowing by anisotropic oxidation: The SiC oxidation rate varies according to the crystal orientation being lower along polar faces. This fact has been exploited for lowering the diameter of the vertical to the basal plane SiC nanopilars with a minimum reduction of their length. Thermal oxidation (1150oC wet oxidation) has been employed towards this purpose. The process was successful with only limitation the stability of NWs after the oxide removal when their diameter is lower than 100nm.
Gate dielectrics: Initial experiments with HfO2 layer deposited by Atomic Layer Deposition (ALD) and subsequent top gate metal (Au) deposition resulted in non-conducting horizontal transistors. Therefore, it has been decided to limit the related effort in thermal oxides. Planar MOS capacitors fabricated on 4H-SiC layers exhibited a DIT~8•1011 cm².eV-1.
WP3: The fellow participated in the fabrication of similar devices with Si NWs and has now the know-how to apply this technology in SiC NWFETs.
In addition, a new photolithography mask setup has been designed in order to fabricate modules of 6 GAA SiC NWFETs. SiC NWFETs performance estimations showed the necessity of developing such modules.
WP4: The related work was conducted on three axes:
1) Further investigation of DNA functionnalization (grafting) of SiC NWs in a back-gated NWFET configuration. The formation of top-down (e-beam lithography and plasma etching) horizontal Si NWs and subsequent carbonization to SiC has been investigated by employing SOI substrates. The Si/SiC core /shell configuration would combine cheap Si substrates as well as mature process with SiC chemical stability. The process is under optimization as in the initial experiments the carbonization process resulted in important deterioration of the underneath oxide.
2) The stability of Si and SiC NWs in saline solutions has been studied. Contrary to Si NWs, no diameter reduction of SiC NWs has been observed, which constitutes a clear proof of chemical inertness of SiC NWs.
3) Vertical SiC NWs are investigated as a solution for increasing the signal of intercortical neural interface (INI) probes for improving longevity of brain-machine interfaces. Indeed, forming arrays of SiC NWs in the detecting region would increase the detecting surface and the corresponding electrical signal.
