Periodic Reporting for period 3 - OCEAN12 (Opportunity to Carry European Autonomous driviNg further with FDSOI technology up to 12nm node)
Okres sprawozdawczy: 2020-06-01 do 2021-05-31
OCEAN12 is a major “Opportunity to Carry European Autonomous driviNg further with FDSOI technology up to 12nm node" and leverage Europe leadership on Automotive and aeronautics applications.
Since the last few years, electronic components become more and more prevalent in the automotive industry. Today they create a superior value for the final customer and represent an important vector of differentiation in this industry. The share economy model, which drives innovation strategies in Smart mobility, will further increase the need for safe, cost efficient, secure, reliable and un-hackable operations, raising logically the proportion of electronics and software as a percentage of the total cost of a vehicle.
OCEAN12 aims to bring very concrete technological solutions and corresponding demonstrators to the key societal challenge of Smart mobility. Based on the innovative FDSOI technology, OCEAN12 will develop new processors and applications design that leverage Fully Depleted Silicon On Insulator (FD-SOI) technology to offer the industry’s lowest power consuming processor and components, especially for automotive and aeronautic applications.
OCEAN12 will develop a technology platform benefitting from FDSOI design’s extreme low leakage and operating voltage (Vdd) scalability attained thank to reverse and forward body biasing (RBB/FBB) of the integrate circuit and its power system architecture. This high performance, low power solution will enable the next strategic generations of smart vehicles. This platform will rely on:
• a pilot line facility capable to manufacture advanced substrates compatible with 12FDX technology,
• the definition of path finding solutions to push 12FDX technology performances and substrates solutions for innovative sensors,
• the development of innovative designs at the forefront of state of the art to enhance FDSOI capacity and guarantee the highest level of integrated solutions,
• the manufacturing of high performance ICs using all palette of FDSOI technologies,
The produced highly integrated, reliable, ultra-low power and lower cost components will be integrated in complex embedded systems accessible to TIER-1, 2 and OEMs and answering strategic challenges of future autonomous vehicles generations (land or air). Several product demonstrators are targeted: high end microcontroller plug and play board, high performance sensors data fusion, highly integrated low power video processing, awaking systems.
A strong added value network is created across this project to enhance a competitive European value chain on a European breakthrough and secure a unique FDSOI roadmap beyond the 22FDX.
OCEAN 12 finally highlights Europe’s unique leading position on FDSOI technology integrating the entire manufacturing chain in this dynamic, from substrate suppliers and foundries to TIER-1 and OEM, involving academia and RTO’s.
Since the last few years, electronic components become more and more prevalent in the automotive industry. Today they create a superior value for the final customer and represent an important vector of differentiation in this industry. The share economy model, which drives innovation strategies in Smart mobility, will further increase the need for safe, cost efficient, secure, reliable and un-hackable operations, raising logically the proportion of electronics and software as a percentage of the total cost of a vehicle.
OCEAN12 aims to bring very concrete technological solutions and corresponding demonstrators to the key societal challenge of Smart mobility. Based on the innovative FDSOI technology, OCEAN12 will develop new processors and applications design that leverage Fully Depleted Silicon On Insulator (FD-SOI) technology to offer the industry’s lowest power consuming processor and components, especially for automotive and aeronautic applications.
OCEAN12 will develop a technology platform benefitting from FDSOI design’s extreme low leakage and operating voltage (Vdd) scalability attained thank to reverse and forward body biasing (RBB/FBB) of the integrate circuit and its power system architecture. This high performance, low power solution will enable the next strategic generations of smart vehicles. This platform will rely on:
• a pilot line facility capable to manufacture advanced substrates compatible with 12FDX technology,
• the definition of path finding solutions to push 12FDX technology performances and substrates solutions for innovative sensors,
• the development of innovative designs at the forefront of state of the art to enhance FDSOI capacity and guarantee the highest level of integrated solutions,
• the manufacturing of high performance ICs using all palette of FDSOI technologies,
The produced highly integrated, reliable, ultra-low power and lower cost components will be integrated in complex embedded systems accessible to TIER-1, 2 and OEMs and answering strategic challenges of future autonomous vehicles generations (land or air). Several product demonstrators are targeted: high end microcontroller plug and play board, high performance sensors data fusion, highly integrated low power video processing, awaking systems.
A strong added value network is created across this project to enhance a competitive European value chain on a European breakthrough and secure a unique FDSOI roadmap beyond the 22FDX.
OCEAN 12 finally highlights Europe’s unique leading position on FDSOI technology integrating the entire manufacturing chain in this dynamic, from substrate suppliers and foundries to TIER-1 and OEM, involving academia and RTO’s.
WP1 main highlights are:
- signature of AMD#3 and the extension of 9 months of the project required by the CoViD19 pandemic impact in 2020 / 2021.
- signature of PCA
- very dense virtual dissemination supported by D&R
WP2: the substrate pilot line enabled the sampling of a generation 2 of FD-SOI substrates and is inline for the final qualification by GF.
A Gen 3 of substrates is under investigations and preliminary proof of concept could be presented in the last review.
On the equipment side: EVG tool will be completed beginning of 2022 and UNITY SC, which has achieved its initial targets explores capabilities and limits of their DRM tool beyond FDSOI to maximize future commercial impact.
Characterization work and technology bricks development lead by CEA-Leti in the task 2 are in line.
The extension of the project by 9 months is far sufficient and no issue is expected.
WP3: in total, all 4 due deliverables have been achieved and uploaded to ECAS.
D3.6 was submitted on time. As the WP leader was on 2-month parental leave (June/July), it could not be reviewed and resulted in delay to upload the deliverable to ECAS portal.
D3.10 was received in January 2021 and uploaded.
The delay of D3.10 is in line with the announcement in Period 2 review. Unfortunately, this has been overseen to be modified in the proposal during the latest amendment. Hence, now appearing as an extra delay.
For D3.13 as the tape outs of various circuits of GNSS receiver are asynchronous in schedule, the validation results of all blocks were not fully available at the time of the writing. Therefore, D3.13 had been deposited with partial validation results of the blocks which were validated. The full range of results will be submitted in the final deliverable of this task. This has been done to prevent delaying the deliverable for the missing some partial sub-block results. Therefore, D3.13 has an additional 3 months delay compared to the initially announced 3-month delay in Period 2 review.
The deliverable D3.8 have several contributors, except for WUT all results/writing of the partners were available in time.
WP4: Always-on and wake-up (Task 4.1) main initial activities are completed, prototyping and measure are starting. Work on algorithmic enablers for future HW-light (Task 4.1.1) wake-up imager has been completed by CEA. In Task 4.1.2 for shock-based wake up, Bosch has completed the full equipment on real car with shock sensors and associated processing: measures still ongoing. A new board have been designed with new sensors, to be used in final demonstrator. Bosh also completed the PCB design for a sound-based wake-up and completed characterization of a packaged microphone sample while EKUT has prototyped its wake-up system including neural network accelerator. In Task 4.1.3 CEA has achieved asynchronous cells design to complete integration of the Ultra-Low power MCU. TUD has completed measurements of the wakeup receiver system.
For sensors subsystems (Task 4.2) Bosch has successfully completed the evaluation of the radar sensor system-on-chip with no further work planned in WP4. For the OFDM radar system, circuit tape out was done in January 2021 and prototypes in June 2021. Finally FhG has prototyped the AlinQ companion chip (Task 4.2.3) and completed the prototype board to support FPGA and ASIC implementations.
In Task 4.3 both Kalray and ST have been able to restart activity based on new plans from amendment # 2 and #3. Kalray and Dolphin (in Task 4.3.1) have completed the physical implementation of a 4 core MPPA cluster on 22FDX technology and performance evaluation, while ST, in Task 4.3.2 has continued design of analogue IPs for MCU in 18nm FDSOI and processed initial prototypes.
For the WP5, the demonstrators’ development is not synchronized among the tasks, but they are all progressing toward the realization of the first demonstration and at good point.
In the next period the main challenge will be to compensate for the accumulated delays and to continue with the development of the demonstrators, even though the agreed extension of 9 months is planned to fit the postponements.
- signature of AMD#3 and the extension of 9 months of the project required by the CoViD19 pandemic impact in 2020 / 2021.
- signature of PCA
- very dense virtual dissemination supported by D&R
WP2: the substrate pilot line enabled the sampling of a generation 2 of FD-SOI substrates and is inline for the final qualification by GF.
A Gen 3 of substrates is under investigations and preliminary proof of concept could be presented in the last review.
On the equipment side: EVG tool will be completed beginning of 2022 and UNITY SC, which has achieved its initial targets explores capabilities and limits of their DRM tool beyond FDSOI to maximize future commercial impact.
Characterization work and technology bricks development lead by CEA-Leti in the task 2 are in line.
The extension of the project by 9 months is far sufficient and no issue is expected.
WP3: in total, all 4 due deliverables have been achieved and uploaded to ECAS.
D3.6 was submitted on time. As the WP leader was on 2-month parental leave (June/July), it could not be reviewed and resulted in delay to upload the deliverable to ECAS portal.
D3.10 was received in January 2021 and uploaded.
The delay of D3.10 is in line with the announcement in Period 2 review. Unfortunately, this has been overseen to be modified in the proposal during the latest amendment. Hence, now appearing as an extra delay.
For D3.13 as the tape outs of various circuits of GNSS receiver are asynchronous in schedule, the validation results of all blocks were not fully available at the time of the writing. Therefore, D3.13 had been deposited with partial validation results of the blocks which were validated. The full range of results will be submitted in the final deliverable of this task. This has been done to prevent delaying the deliverable for the missing some partial sub-block results. Therefore, D3.13 has an additional 3 months delay compared to the initially announced 3-month delay in Period 2 review.
The deliverable D3.8 have several contributors, except for WUT all results/writing of the partners were available in time.
WP4: Always-on and wake-up (Task 4.1) main initial activities are completed, prototyping and measure are starting. Work on algorithmic enablers for future HW-light (Task 4.1.1) wake-up imager has been completed by CEA. In Task 4.1.2 for shock-based wake up, Bosch has completed the full equipment on real car with shock sensors and associated processing: measures still ongoing. A new board have been designed with new sensors, to be used in final demonstrator. Bosh also completed the PCB design for a sound-based wake-up and completed characterization of a packaged microphone sample while EKUT has prototyped its wake-up system including neural network accelerator. In Task 4.1.3 CEA has achieved asynchronous cells design to complete integration of the Ultra-Low power MCU. TUD has completed measurements of the wakeup receiver system.
For sensors subsystems (Task 4.2) Bosch has successfully completed the evaluation of the radar sensor system-on-chip with no further work planned in WP4. For the OFDM radar system, circuit tape out was done in January 2021 and prototypes in June 2021. Finally FhG has prototyped the AlinQ companion chip (Task 4.2.3) and completed the prototype board to support FPGA and ASIC implementations.
In Task 4.3 both Kalray and ST have been able to restart activity based on new plans from amendment # 2 and #3. Kalray and Dolphin (in Task 4.3.1) have completed the physical implementation of a 4 core MPPA cluster on 22FDX technology and performance evaluation, while ST, in Task 4.3.2 has continued design of analogue IPs for MCU in 18nm FDSOI and processed initial prototypes.
For the WP5, the demonstrators’ development is not synchronized among the tasks, but they are all progressing toward the realization of the first demonstration and at good point.
In the next period the main challenge will be to compensate for the accumulated delays and to continue with the development of the demonstrators, even though the agreed extension of 9 months is planned to fit the postponements.
FDSOI substrates developed in terms of uniformity and defectgivity,
Process and metrology technologies including plasma bonding and DRM,
Shock based and sound based always on wake up systems,
1st fast-chirp Radar chip in 22FDX technology,
New SW framework (KaF, Kalray Framework) and innovative neural network approach (KaNN, Kalray Neural Networks) for the high efficiency embedded computing design solution,
Process and metrology technologies including plasma bonding and DRM,
Shock based and sound based always on wake up systems,
1st fast-chirp Radar chip in 22FDX technology,
New SW framework (KaF, Kalray Framework) and innovative neural network approach (KaNN, Kalray Neural Networks) for the high efficiency embedded computing design solution,