Automated, Fast Generation of High-Performance Instruction Set Simulators for Microprocessors

Informacje na temat projektu

HIPERSIM

Identyfikator umowy o grant: 877543

DOI

10.3030/877543

Projekt został zamknięty

Data podpisania przez KE 2 Lipca 2019

Data rozpoczęcia 1 Sierpnia 2019

Data zakończenia 31 Stycznia 2020

Finansowanie w ramach

• INDUSTRIAL LEADERSHIP - Innovation In SMEs

Koszt całkowity

€ 71 429,00

Wkład UE

€ 50 000,00

Koordynowany przez

ABIX GMBH
Austria

Periodic Reporting for period 1 - HIPERSIM (Automated, Fast Generation of High-Performance Instruction Set Simulators for Microprocessors)

Okres sprawozdawczy: 2019-08-01 do 2020-01-31

Podsumowanie kontekstu i ogólnych celów projektu

The development of microprocessors is a complex, time and effort consuming process. Every microprocessor architecture requires specific software development tools in order to develop programs that can be executed on this processor. Program development includes that a program can be tested to be working for the respective processor hardware. To make best use of the significant time that elapses between the availability of the specification for a new microprocessor architecture and the availability of the microprocessor hardware, software simulation tools can be used that mimic the behavior of the coming hardware. Thus, program development can be started and performed very early and without the need to verify the program on hardware.

However, also the creation of software simulation tools is usually a manual, complex and time-consuming process. To reduce the efforts and risks involved in simulator development ABIX is developing the HIPERSIM (high-performance simulation) framework. The ABIX HIPERSIM framework includes a generator tool that reads in a microprocessor's architecture description and converts it automatically into source code for a corresponding simulator tool. Together with pre-built library modules, that include a high-performance simulation engine as well as a large palette of performance features, performant simulators can be auto-generated from a microprocessor specification with very little effort and in a short time frame for a great variety of microprocessor families.

For companies designing new or modifying existing microprocessor architectures it is expedient to prepare for a smooth production and market entry of the microprocessor hardware. At that the design and evaluation of the microprocessor's instruction set is of supreme importance. While hardware designers need to quickly test new ideas without bearing the time and costs for several hardware creation cycles, software engineers need development tools and need to develop application programs at an early stage. These objectives can be ideally supported by the ABIX HIPERSIM framework before any microprocessor hardware is produced and is becoming available on the market. Thus, by using HIPERSIM hardware designers can avoid costly redesign cycles and software developers get a head start on developing programs for upcoming microprocessors.

Prace wykonane od początku projektu do końca okresu sprawozdawczego oraz najważniejsze dotychczasowe rezultaty

"To assess the technical and economic feasibility and the potential of the ABIX HIPERSIM framework ABIX has performed a feasibility study. This study included work packages to assess external factors as the intellectual property situation including patents and prior-art, the competitive landscape, as well as a market analysis. In addition to this external aspects the feasibility study was looking at company internal factors in the form of a SWOT analysis, a risk analysis, an evaluation of the organizational strengths and weaknesses, and an analysis of the economic situation and roadmap. To collect feedback about the HIPERSIM technological concept and its acceptance to potential customers, ABIX has performed a small field study among existing and potential customers and consultants.

Based on the data collected during the feasibility study ABIX could gain new insights into all aspects of this study and could on that score improve and strengthen action items and road maps for technical and economic roadmaps. A prominent result from the SWOT and risk analyses was the reformulation and condensation of the ""sustainable differentiations"" that ABIX can mobilize for customers. From the feedback of the field study the ""unique product selling points"" for the HIPERSIM framework as well as the technological roadmap for the framework components were improved and enhanced. In particular the field study helped to identify common feature and concept items requirements for the technical roadmap. As a major result from the business coaching provided with the study effort a new ""customer segment"" could be identified which had not yet been in focus. Also, the targets for market entry, market regional focus, and technical trends were significantly improved due to the business coaching workshops performed. Regarding the business model new insights could be gained in terms of the restructuring of the licensing and maintenance models intended for the software products and in terms of staff requirements for development, support & maintenance, and marketing & sales. With these inputs the business model calculations were reiterated and solidified."

Innowacyjność oraz oczekiwany potencjalny wpływ (w tym dotychczasowe znaczenie społeczno-gospodarcze i szersze implikacje społeczne projektu)

The evaluation of existing IP in form of patents and prior-art documents (e.g. scientific papers) as well as the competitive analysis indicated good clearance between the concepts of HIPERSIM in comparison with existing concepts and products. The automatic generation of a software development tool, in particular a tool which is capable of simulating a microprocessor with the level of detail and the performance of a HIPERIM simulator, is not generally available or has limitations which are not an issue with HIPERSIM. A primary goal for wide-ranging applicability of HIPERSIM is the support for a broad variety of microprocessor architecture descriptions and of architecture variants and their specific features and thus the capability to generally reduce simulator generation time and to minimize the need for any manual intervention in the generation process.

The HIPERSIM prototype is targeted at the RISC-V microprocessor architecture. RISC-V is an open source instruction set that becomes more and more popular as a true alternative to commercially licensed microprocessor hardware or IP. The RISC-V instruction set specification includes a basic instruction set definition as well as a customizable range of instructions which can be adapted to customers' and end users' requirements. A simulator based on HIPERSIM can significantly contribute to the evolution of microprocessor eco-systems like RISC-V. This ranges from simple cost reductions in hardware and software development cycles and shortening of the time-to-market timeframes to more globally relevant aspects. For instance, the support of the European Processor Initiative (EPI) with the goal to create and establish a low-power and high performance microprocessor architecture based on European know-how. This initiative shall strengthen the competitiveness and leadership of European industry and science by becoming independent of patented and/or licensed microprocessor IP, hardware, and tools provided from outside of Europe. The EPI accelerator stream is based on leveraging the RISC-V instruction set architecture and specification.

Moreover, ABIX is participating in an EU ITEA3 research program with the goal to establish a platform modelling concept for IoT systems hardware and software. In that context the ABIX HIPERSIM simulator is used by research partners for the dynamic estimation of code optimizations and power consumptions applied by an experimental compiler tool. The project itself might yield vital impacts on how IoT systems of different scales are being cost- and time-efficiently designed and developed in the future.

Conceptual illustration of the ABIX HIPERSIM platform, components, and work-flows.