Periodic Reporting for period 1 - NADIA (Novel approach to Area selective Deposition for BEOL Interconnect Applications)
Okres sprawozdawczy: 2020-09-01 do 2022-08-31
Area selective deposition has been hailed as the next paradigm shift in nanoscale patterning as we continue the down scaling trend of Moore’s Law. As feature sizes get smaller, traditional “top-down” photolithography steps are struggling to fabricate the critical dimensions needed in devices. ASD has been proposed as a “bottom-up” technique which could see Moore’s Law continue for several more technology nodes and even into new 3D device architectures. In an ASD process a material is preferentially deposited, usually by atomic layer deposition (ALD), on a specific area on the surface while the remainder is left uncoated, giving control over the deposited thin film in the horizontal plane. One approach being adopted to achieve ASD is through the use of self- assembled monolayers (SAMs), which can assist in the patterning of microscale and nanoscale features. The adaptability of the SAM chemistry makes them a prime candidate for selectively adhesion to particular sections of the surface, allowing them to block any subsequently deposited material. The primary goal of the NADIA project was to develop a fully self-aligned (ASD) concept based on Dielectric-on-Dielectric (DoD) or Dielectric-on-Metal (DoM) without involving hard mask or resist steps and to downscale the concept to features with critical dimensions below 50 nm. In other words, a particular SAM was deposited on a metal surface, where deposition would be blocked, leaving the dielectric free for deposition. This is the called the DoD scheme. In the DoM scheme a SAM was deposited that would passivate the dielectric area, leaving the metal free for deposition.
The project has achieved most of its objectives, milestones, and deliverables within the planned period with relatively minor deviations. The main focus of the NADIA project was to deepen our understanding of the fundamentals of ASD processing and to use this understanding to improve upon the state-of-the-art. There were four main objectives in NADIA which were grouped into three work packages:
(i) Establish a method for sample preparation (WP1)
(ii) Characterising the functionalization of the metal and dielectric surfaces (WP2)
(iii) Dielectric on Dielectric and Dielectric on Metal nanometre patterning using ASD (WP3)
(iv) Adaption to industry fabrication process (WP3)
The project has achieved most of its objectives, milestones, and deliverables within the planned period with relatively minor deviations. The main focus of the NADIA project was to deepen our understanding of the fundamentals of ASD processing and to use this understanding to improve upon the state-of-the-art. There were four main objectives in NADIA which were grouped into three work packages:
(i) Establish a method for sample preparation (WP1)
(ii) Characterising the functionalization of the metal and dielectric surfaces (WP2)
(iii) Dielectric on Dielectric and Dielectric on Metal nanometre patterning using ASD (WP3)
(iv) Adaption to industry fabrication process (WP3)
Work Package 1: Surface preparation and control – the main task for this WP was to investigate and quantify the effect of pre-treatment on dielectric and metal surfaces for optimum SAM grafting. UV ozone exposure was used to remove organic material and reduce carbon contamination of Si oxide surfaces while also generating -OH groups which would generate more sites for SAM bonding. Interestingly, a difference in the optimum duration to UV exposure was observed between a Si substrate with a native oxide present and for a 50 nm grown Si oxide. The spin-on dielectric was solvent sensitive and was predominantly carbon and fluorine based making it incompatible with SAM processing. However, the surface could successfully be passivated by a 30s C4F8 plasma treatment.
Work Package 2: Surface functionalization with SAMs – the main task for this work WP was to optimize the SAM formation on the pre-treated surfaces and investigate the stability of the SAM layer during an ALD process. Investigation of SAM formation from different deposition methods (liquid vs vapour) was performed, by comparing thickness of the deposited SAM layer and by chemical analysis using XPS and FTIR. Degradation of SAMs during the ALD cycle leads to loss of selectivity during the process. To investigate the mechanisms behind selectivity loss, both in-situ and in-operando experiments were performed on SAM layers, including at the synchrotron facility, Diamond Light Source in the UK. This was an extremely import part of the project as it allowed for chemical analysis to be performed while the SAM experienced conditions similar to that of an ALD chamber.
Work Package 3: ASD Dielectric on Dielectric and Dielectric on Metal – this work package contained two of the outlined objectives. The first objective was focused on successfully demonstrating an ASD process on blanket layers. In the DoM scheme a 30 s C4F8 plasma is shown to block deposition of HfO2 and TiO2 films, from tetrachloride precursors, on a spin-on dielectric material used in 3D devices. In the DoD scheme, Al silicate was successfully deposited on a Si oxide while being effectively blocked on the Cu area.
The second object was to downscale the successfully ASD process to critical dimensions used in devices. In the DoM scheme, a 3D architecture was investigated with a proprietary spin on dielectric and Cu lines. Through corrosion and reliability testing it was found that 9 nm of HfO2 was capable of preventing Cu oxidation in the RDLs. This is one of the thinnest oxide barriers recorded in the literature. Currently, reliability testing and corrosion tests are being performed on TiO2 layers with the aim that it will also be capable of preventing Cu oxidation in RDLs.
For the DoD scheme it was demonstrated how Al silicate could be selectively deposited in a low temperature ALD process on 50 nm wide Cu/SiO2. The Al silicate has a lower k-value than Al oxide but has similar electrical properties, making it an attractive alternative for fully self-aligned vias (FSAV).
Project Management and Training Activities: In addition to the research activities outlined above, the fellow has taken part in and attended several training courses covering a range of areas. Some of the training activities focused on the research aspects while others were tailored toward project management and improving presentation skills. Due to the interdisciplinary nature of the project the fellow was able to expand her scope of interest and had the ability to interact with colleagues from the wider IMEC community and from industry.
Work Package 2: Surface functionalization with SAMs – the main task for this work WP was to optimize the SAM formation on the pre-treated surfaces and investigate the stability of the SAM layer during an ALD process. Investigation of SAM formation from different deposition methods (liquid vs vapour) was performed, by comparing thickness of the deposited SAM layer and by chemical analysis using XPS and FTIR. Degradation of SAMs during the ALD cycle leads to loss of selectivity during the process. To investigate the mechanisms behind selectivity loss, both in-situ and in-operando experiments were performed on SAM layers, including at the synchrotron facility, Diamond Light Source in the UK. This was an extremely import part of the project as it allowed for chemical analysis to be performed while the SAM experienced conditions similar to that of an ALD chamber.
Work Package 3: ASD Dielectric on Dielectric and Dielectric on Metal – this work package contained two of the outlined objectives. The first objective was focused on successfully demonstrating an ASD process on blanket layers. In the DoM scheme a 30 s C4F8 plasma is shown to block deposition of HfO2 and TiO2 films, from tetrachloride precursors, on a spin-on dielectric material used in 3D devices. In the DoD scheme, Al silicate was successfully deposited on a Si oxide while being effectively blocked on the Cu area.
The second object was to downscale the successfully ASD process to critical dimensions used in devices. In the DoM scheme, a 3D architecture was investigated with a proprietary spin on dielectric and Cu lines. Through corrosion and reliability testing it was found that 9 nm of HfO2 was capable of preventing Cu oxidation in the RDLs. This is one of the thinnest oxide barriers recorded in the literature. Currently, reliability testing and corrosion tests are being performed on TiO2 layers with the aim that it will also be capable of preventing Cu oxidation in RDLs.
For the DoD scheme it was demonstrated how Al silicate could be selectively deposited in a low temperature ALD process on 50 nm wide Cu/SiO2. The Al silicate has a lower k-value than Al oxide but has similar electrical properties, making it an attractive alternative for fully self-aligned vias (FSAV).
Project Management and Training Activities: In addition to the research activities outlined above, the fellow has taken part in and attended several training courses covering a range of areas. Some of the training activities focused on the research aspects while others were tailored toward project management and improving presentation skills. Due to the interdisciplinary nature of the project the fellow was able to expand her scope of interest and had the ability to interact with colleagues from the wider IMEC community and from industry.
Established a robust method for surface preparation for SAMs grafting by utilising UV ozone exposure.
Used NAP-XPS to recreate in-operando conditions usually seen by SAMs in an ALD chamber to look at degradation mechanisms.
Demonstrated that Al silicate films can be deposited selectively for the DoD scheme on 50 nm Cu/SiO2 lines.
Proved that a 9 nm HfO2 barrier layer was capable of preventing Cu oxidation in RDLs.
Demonstrated for the first time an ASD process, using TiO2, that is compatible with 3D integration.
Used NAP-XPS to recreate in-operando conditions usually seen by SAMs in an ALD chamber to look at degradation mechanisms.
Demonstrated that Al silicate films can be deposited selectively for the DoD scheme on 50 nm Cu/SiO2 lines.
Proved that a 9 nm HfO2 barrier layer was capable of preventing Cu oxidation in RDLs.
Demonstrated for the first time an ASD process, using TiO2, that is compatible with 3D integration.