Periodic Reporting for period 1 - StorAIge (Embedded storage elements on next MCU generation ready for AI on the edge)
Okres sprawozdawczy: 2021-07-01 do 2022-06-30
The main objective of the StorAIge project is the development and industrialization of FDSOI 28nm and next generation embedded Phase Change Memory (ePCM) world-class semiconductor technologies, allowing the prototyping of high performance, Ultra low power and secured & safety System on Chip (SoC) solutions enabling competitive Artificial Intelligence (AI) for Edge applications. The main challenge addressed by the project is on one hand to handle the complexity of sub-28nm ‘more than moore’ technologies and to bring them up at a high maturity level and on the other hand to handle the design of complex SoCs for more intelligent, secure, flexible, low power consumption and cost effective system applications. The project is targeting chipset and solutions with very efficient memories and high computing power targeting 10 Tops per Watt.
The development of the most advanced automotive microcontrollers in FDSOI 28nm ePCM will be the main stream to demonstrate the high performance and the robustness of the ePCM solution. The next generation of FDSOI ePCM will target general purpose advanced microcontrollers usable for large volume Edge AI application in industrial and consumer markets with the best compromise on three requirements: performances, low power and adequate security.
On top of the development and industrialization of silicon process lines and SoC design, StorAIge will also address new design methodologies and tools to facilitate the exploitation of these advanced technology nodes, particularly for high performance microcontrollers having AI capabilities. Activities will be performed to setup robust and adequate Security and Safety level in the final applications, defining and implementing the good ‘mixture’ and tradeoff between HW and SW solutions to speed up adoption for large volume applications.
The development of the most advanced automotive microcontrollers in FDSOI 28nm ePCM will be the main stream to demonstrate the high performance and the robustness of the ePCM solution. The next generation of FDSOI ePCM will target general purpose advanced microcontrollers usable for large volume Edge AI application in industrial and consumer markets with the best compromise on three requirements: performances, low power and adequate security.
On top of the development and industrialization of silicon process lines and SoC design, StorAIge will also address new design methodologies and tools to facilitate the exploitation of these advanced technology nodes, particularly for high performance microcontrollers having AI capabilities. Activities will be performed to setup robust and adequate Security and Safety level in the final applications, defining and implementing the good ‘mixture’ and tradeoff between HW and SW solutions to speed up adoption for large volume applications.
The StorAIge project started in July 2021, the kickoff was held remotely at the beginning of July. The partners and teams had the opportunity to present their respective work plans and short-term deadlines. The first collaborative actions were defined in more detail (wafers exchange, samples exchange, specifications sharing...). Very soon the actions were focused on the definition of the requirements for the different demonstrators including 15 use cases. This first year has allowed to better define the development to be done and the needs and specifications of the systems and sub-systems. The evaluation of the computing and memory requirements was defined for the different use cases in WP2 and regularly reviewed by the expert committee appointed in this work package.
The first interactions were facilitated by the fact that 50% of the consortium was used to working together on the previous WAKeMeUP project. Regarding silicon, the progress on PCM lines is important. The 28nm ePCM has undergone major qualification on its basic perimeter. Various back-ends are being developed. To support the increase in yield, prototypes have been launched in manufacturing, notably by ST's automotive group with a first prototype circuit, the 'SR6P6' chip A. The first silicon has been manufactured and the first tests are very conclusive. On the other memory technologies (OxRAM and FeRam), progress has also been made even if the planning of the major deliverables will take place a little later in the project.
On the next technological node in 18nm, a first set of IP libraries design has been completed, the next step will concern an enrichment of the base platform. In parallel to these process development activities, the design teams of the ST microcontroller groups are focused on the design of an advanced microcontroller circuit for Artificial Intelligence. Tape Out is planned for the last quarter of 2022.
A lot of work has been done at the application level to ‘caracterize’ and 'standardise' the demonstrators of the project. An ID card has been filled in for each application demonstrator, and a more precise follow-up (with MDTA) is being put in place to better monitor relative progress.
Globally the project is in good track and in a ‘crusing’ mode, no deviation so far has been anticipated.
The first interactions were facilitated by the fact that 50% of the consortium was used to working together on the previous WAKeMeUP project. Regarding silicon, the progress on PCM lines is important. The 28nm ePCM has undergone major qualification on its basic perimeter. Various back-ends are being developed. To support the increase in yield, prototypes have been launched in manufacturing, notably by ST's automotive group with a first prototype circuit, the 'SR6P6' chip A. The first silicon has been manufactured and the first tests are very conclusive. On the other memory technologies (OxRAM and FeRam), progress has also been made even if the planning of the major deliverables will take place a little later in the project.
On the next technological node in 18nm, a first set of IP libraries design has been completed, the next step will concern an enrichment of the base platform. In parallel to these process development activities, the design teams of the ST microcontroller groups are focused on the design of an advanced microcontroller circuit for Artificial Intelligence. Tape Out is planned for the last quarter of 2022.
A lot of work has been done at the application level to ‘caracterize’ and 'standardise' the demonstrators of the project. An ID card has been filled in for each application demonstrator, and a more precise follow-up (with MDTA) is being put in place to better monitor relative progress.
Globally the project is in good track and in a ‘crusing’ mode, no deviation so far has been anticipated.
By putting together key players of the AI value chain, StorAIge will help to predict and define what tasks AI will be applied to tomorrow, at the edge devices with a special focus on Automotive, Industrial/Consumer and Secure applications, providing the best-in-class silicon-based solutions.
StorAIge is pursuing a short and middle term R&D program to explore introduction of the following technologies into products with a multidisciplinary approach:
• Neural Networks have emerged as a powerful complementary tool to augment systems with more complex functionality
• Classical approaches of digital HW architectures already hitting a wall in terms of memory bandwidth and compute density
• Quantized and Binary Neural Networks offer a step forward in terms of complexity and energy consumption reduction
•In Memory Compute (IMC) is seen as the most promising technology forward that requires a multidisciplinary approach to be successful o Materials o New devices (e.g. PCM cells)
o New macro-cells structures (IMC)
o New ways of thinking applications, systems and ad-hoc training
• Analog IMC promises another order of magnitude for compute and power densities.
The main goal in StorAIge is to achieve ASIC comparable efficiency by exploiting different eNVM technologies (FD-SOI 28nm PCM, OxRAM, FeRAM) and configurable accelerators. Many of these accelerators and their design methodologies are already at high TRL level. By applying them to 15 concrete industrial use cases in a state-of-the-art technology and leveraging the ePCM / NVM, StorAIge will create a complete ecosystem of technology, architecture, design method and applications to address the extreme energy efficiency, security, and safety needs of enterprise class of edge AI systems.
The ambition of the project is therefore geared towards these use cases that concentrate improved or new functionalities and represent a significant integration challenge.
StorAIge is pursuing a short and middle term R&D program to explore introduction of the following technologies into products with a multidisciplinary approach:
• Neural Networks have emerged as a powerful complementary tool to augment systems with more complex functionality
• Classical approaches of digital HW architectures already hitting a wall in terms of memory bandwidth and compute density
• Quantized and Binary Neural Networks offer a step forward in terms of complexity and energy consumption reduction
•In Memory Compute (IMC) is seen as the most promising technology forward that requires a multidisciplinary approach to be successful o Materials o New devices (e.g. PCM cells)
o New macro-cells structures (IMC)
o New ways of thinking applications, systems and ad-hoc training
• Analog IMC promises another order of magnitude for compute and power densities.
The main goal in StorAIge is to achieve ASIC comparable efficiency by exploiting different eNVM technologies (FD-SOI 28nm PCM, OxRAM, FeRAM) and configurable accelerators. Many of these accelerators and their design methodologies are already at high TRL level. By applying them to 15 concrete industrial use cases in a state-of-the-art technology and leveraging the ePCM / NVM, StorAIge will create a complete ecosystem of technology, architecture, design method and applications to address the extreme energy efficiency, security, and safety needs of enterprise class of edge AI systems.
The ambition of the project is therefore geared towards these use cases that concentrate improved or new functionalities and represent a significant integration challenge.